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Simulink Blocks Supported for Range Analysis

Overview of Simulink Block Support

The following tables summarize range analysis support for Simulink® blocks. Each table lists all the blocks in each Simulink library and describes support information for that particular block. If the software does not support a given block, where possible, automatic stubbing considers the interface of the unsupported blocks, but not their behavior, during the analysis. However, if any of the unsupported blocks affect the simulation outcome, the analysis may achieve only partial results. If the analysis cannot use automatic stubbing for a block, the block is marked as “not stubbable”. For more information, see Automatic Stubbing.

Not all blocks that are supported for range analysis are supported for fixed-point conversion. To check if a block supports fixed-point data types, see Blocks That Do Not Support Fixed-Point Data Types.

 Additional Math and Discrete Library

 Commonly Used Blocks Library

 Continuous Library

 Discontinuities Library

 Discrete Library

 Logic and Bit Operations Library

 Lookup Tables Library

 Math Operations Library

 Model Verification Library

 Model-Wide Utilities Library

 Ports & Subsystems Library

 Signal Attributes Library

 Signal Routing Library

 Sinks Library

 Sources Library

 User-Defined Functions Library

Limitations of Support for Model Blocks

Range analysis supports the Model block with the following limitations. The software cannot analyze a model containing one or more Model blocks if:

  • The referenced model is protected. Protected referenced models are encoded to obscure their contents. This allows third parties to use the referenced model without being able to view the intellectual property that makes up the model.

    For more information, see Reference Protected Models from Third Parties.

  • The parent model or any of the referenced models returns an error when you set the Configuration Parameters > Diagnostics > Connectivity > Element name mismatch parameter to error.

    You can use the Element name mismatch diagnostic along with bus objects so that your model meets the bus element naming requirements imposed by some blocks.

  • The Model block uses asynchronous function-call inputs.

  • Any of the Model blocks in the model reference hierarchy creates an artificial algebraic loop. If this occurs, take the following steps:

    1. On the Diagnostics pane of the Configuration Parameters dialog box, set the Minimize algebraic loop parameter to error so that Simulink reports an algebraic loop error.

    2. On the Model Referencing Pane of the Configuration Parameters dialog box, select the Minimize algebraic loop occurrences parameter.

      Simulink tries to eliminate the artificial algebraic loop during simulation.

    3. Simulate the model.

    4. Simulink will remove the algebraic loop if possible. If Simulink cannot eliminate the artificial algebraic loop, highlight the location of the algebraic loop by opening the Modeling tab and, in the Compile section, clicking Update Model.

    5. Eliminate the artificial algebraic loop so that the software can analyze the model. Break the loop with Unit Delay blocks so that the execution order is predictable.


    For more information, see Algebraic Loop Concepts.

  • The parent model and the referenced model have mismatched data type override settings. The data type override setting of the parent model and its referenced models must be the same, unless the data type override setting of the parent model is Use local settings. You can configure data type override settings to simulate a model that specifies fixed-point data types. Using this setting, the software temporarily overrides data types with floating-point data types during simulation.

    For more information, see set_param.

    To observe the true behavior of your model, set the data type override parameter to UseLocalSettings or Off.


  • The referenced model is a Model block with virtual buses at input ports, and the signals in the bus do not all have the same sample time at compilation. To make the model compatible with Simulink Design Verifier analysis, convert the virtual bus to a nonvirtual bus, or specify an explicit sample time for the port.

  • When you run the analysis on Model block, then the code generated as a top model is not supported.

  • The referenced model is in referenced mode and the model block has periodic event ports enabled. For more information, see Schedule rates with.