Sign

Indicate sign of input

• 

Libraries:
Simulink / Math Operations
HDL Coder / HDL Floating Point Operations
HDL Coder / Math Operations

Description

For real inputs, the Sign block outputs the sign of the input:

Input	Output
Greater than zero	1
Equal to zero	0
Less than zero	–1

When the input u is a complex scalar, the block output matches the MATLAB^® result for:

sign(u) = u./ abs(u)

(1)

Examples

Sign Block Behavior for Real Inputs

This example shows how, for vector and matrix inputs, the block outputs a vector or matrix where each element is the sign of the corresponding input element.

model='ex_sign_block_matrix_input_real.slx';
open_system(model)

Sign Block Behavior for Complex Issues

This example shows how, when an element of a vector or matrix input is complex, the block uses the same formula that applies to scalar input.

model='ex_sign_block_matrix_input_complex.slx';
open_system(model)

Extended Examples

Model Fault-Tolerant Fuel Control System

Combine Stateflow® and Simulink® capabilities to model hybrid systems. This type of modeling is particularly useful for systems that have numerous possible operational modes based on discrete events. Traditional signal flow is handled in Simulink while changes in control configuration are implemented in Stateflow. The model described in this example represents a fuel control system for a gasoline engine. The system is robust in that it detects individual sensor failures, and the control system is dynamically reconfigured for uninterrupted operation.

• Open Model

Model Stick-Slip Friction and Hard Stops in Mass-Spring-Damper System

One way you can incorporate hard stops and friction changes from stick-slip motion into a mass-spring-damper model.

• Open Live Script

Ports

Input

Port_1 — Input signal

scalar | vector | matrix

Input signal whose sign will determine the output.

The block supports complex input signals only for floating-point data types, double and single.

Data Types: single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | Boolean | fixed point
Complex Number Support: Yes

Output

Port_1 — Output signal

scalar | vector | matrix

Output signal that is the sign of the input signal.

Data Types: single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | Boolean
Complex Number Support: Yes

Parameters

Enable zero-crossing detection — Enable zero-crossing detection

on (default) | off

Select to enable zero-crossing detection. For more information, see Zero-Crossing Detection.

Programmatic Use

Block Parameter: ZeroCross

Type: character vector | string

Values: 'off' | 'on'

Default: 'on'

Sample time (-1 for inherited) — Interval between samples

-1 (default) | scalar | vector

Specify the time interval between samples. To inherit the sample time, set this parameter to -1. For more information, see Specify Sample Time.

Dependencies

This parameter is visible only if you set it to a value other than -1. To learn more, see Blocks for Which Sample Time Is Not Recommended.

Programmatic Use

To set the block parameter value programmatically, use the set_param function.

Parameter:	SampleTime
Values:	"-1" (default) | scalar or vector in quotes

Block Characteristics

Data Types	Boolean | double | fixed point | integer | single
Direct Feedthrough	yes
Multidimensional Signals	no
Variable-Size Signals	no
Zero-Crossing Detection	yes

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation

Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has one default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see OutputPipeline (HDL Coder).

Complex Data Support

This block supports code generation for complex signals.

PLC Code Generation
Generate Structured Text code using Simulink® PLC Coder™.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.

Version History

Introduced before R2006a