MATLAB and Simulink for System Development on AMD Versal Adaptive SoCs

System designers use MATLAB and Simulink to develop, deploy, and verify designs on Versal™ Adaptive SoC devices. You can use MATLAB and Simulink to:

  • Model and simulate hardware architectures and algorithms
  • Deploy systems to Versal Adaptive SoC boards using automatic HDL and C code generation
  • Debug and verify algorithms running on Versal development boards connected to MATLAB and Simulink test environments

Simulating Designs for Versal Adaptive SoC Devices

With SoC Blockset, you can simulate the behavior of Simulink models when deployed to Versal Adaptive SoC devices. This approach enables you to:

  • Partition algorithms between portions to execute on Arm® Cortex®-A72 processors and implement as IP cores in programmable logic
  • Incorporate IP cores into preconfigured reference designs and edit the created model to include the algorithm targeted to the processor
  • Run simulations of hardware/software applications that incorporate the effects of communication between processors, programmable logic, and off-chip DDR memory

Deploying Models to Versal Adaptive SoC Boards

HDL Coder and SoC Blockset provide targeting workflows for Versal Adaptive SoC boards. Using HDL Coder, you can generate IP cores from your algorithm with AXI4 interfaces and deploy them to programmable logic. Then, using Embedded Coder, you can generate software applications with device drivers to communicate with AXI4 interfaces on IP cores.

SoC Blockset provides an integrated hardware/software targeting workflow based on HDL Coder and Embedded Coder. SoC Blockset enables automated customization of boards, daughter cards, OS, and IP.

Using HDL Coder and SoC Blockset targeting workflows, you can:

  • Prototype your design on the Versal AI Core Series VCK190 Evaluation Kit from MATLAB and Simulink
  • Tune AXI4 registers from MATLAB to adjust algorithm parameters interactively on Versal boards
  • Create your own board and reference design definitions for custom Versal-based hardware boards
  • Customize models with predefined internal interfaces, external input/output interfaces, and AXI4 registers

Verifying Deployed Algorithms on Versal Adaptive SoC Hardware

You can verify your HDL code with MATLAB and Simulink testbenches rather than writing Verilog or VHDL testbenches. Verifying the code works by using cosimulation with HDL simulators from Siemens® EDA, Cadence®, and AMD Xilinx®. This process lets you:

  • Verify and test on the Versal AI Core Series VCK190 Evaluation Kit
  • Verify IP cores programmed into the fabric of Versal devices using FPGA-in-the-loop testing
  • Test and debug on hardware using MATLAB to access on-board memory with AXI Manager and FPGA Data Capture


Learn about the products used for system development on Versal Adaptive SoC applications.