Develop SoC Architectures from Specifications
You can start with a functional architecture of your application in System Composer™, and allocate functional components to the SoC hardware architecture (processor), programmable logic (FPGA), and memory. Simulate the behavior of the entire application and verify its functional correctness. Then evaluate the implementation to decide how to allocate its functional components between hardware and software.
Analyze Algorithm Resource Usage
Analyze Simulink models or MATLAB® functions to generate reports summarizing the number of arithmetic operators required for implementation. Use these reports to compare different architectures for FPGA, ASIC, and SoC devices, perform design tradeoffs, and explore hardware/software partitioning.
Model DDR memory and simulate shared memory transactions between hardware logic and embedded processors. Configure DMA memory controllers to arbitrate memory traffic. Account for memory latency and throughput in simulation.
Model task execution of embedded software as managed by the operating system (OS). Simulate tasks with accurate timing, accounting for context switching, task preemption, and execution duration. Model software interrupts generated by FPGA fabric. Apply statistics to simulate nondeterministic task duration, or apply task durations recorded during hardware testing.
SoC Model Templates
Build complete models of SoC applications from scratch using a step-by-step approach, or start from predefined templates for hardware/software coprocessing, including templates for vision and communication applications.
Simulation with Recorded I/O Data
Record hardware peripheral sources such as RF signals or HDMI data, and then play back recordings as sources in simulations or hardware testing.
Task Execution Analysis
Simulate the software system of SoC applications by running Simulink models that incorporate timer-driven and event-driven tasks. Visualize task execution timing, preemption, rate overruns, drops, and core utilization. Replay task executions in simulation using task timing data captured from previous simulations or directly from SoC devices.
DDR Memory Performance
Analyze the memory bandwidth of system designs. Visualize simulation results and bandwidth metrics before deploying to the SoC device.
On-Device Memory Performance Monitoring and Task Execution Profiling
Measure memory performance and task execution on an SoC device, and then visualize and analyze these measurements to tune an SoC model to meet your system performance requirements. Interact in real time with SoC devices from MATLAB or from your Simulink test bench.
Generate Embedded Software Project
When used with Embedded Coder®, SoC Blockset generates complete embedded software projects from models, including schedulers, software tasks, and I/O device driver integration.
Generate Reference Designs
Generate reference designs for programmable logic. Reference designs are configured networks of IP cores with data and control paths that may be connected to external memories and software applications. SoC Blockset connects to Xilinx and Intel design tools to produce bitstreams and then programs FPGA and SoC boards.
Target COTS Boards and Custom Boards
Implement hardware/software applications on supported hardware kits including Xilinx Zynq UltraScale+ MPSoCs and RFSoCs, Zynq-7000 SoCs and Intel Cyclone and Arria SoC FPGAs. Target boards using hardware support packages or build support for custom boards.
Wireless Communications and Radar
Evaluate wireless communications and radar applications while accounting for the effects of processor, FPGA and DDR memory subsystems. Use predefined models of Xilinx Zynq UltraScale+ MPSoC and RFSoC devices to simulate hardware/software applications, then deploy to development boards and configure the data converters of RFSoC devices.
Video and Image Processing
Data-intensive video and image processing applications require designers to assess memory bandwidth requirements to ensure the application’s frame rate and frame size requirements are met. Use SoC Blockset to model external DDR memory and evaluate memory bandwidth dynamically with simulation. Then generate the fully-compliant AXI4 interface IP using HDL Coder™.
Motor and Power Control
Implement real-time motor and power electronics control on multicore microcontrollers or SoCs by partitioning control tasks into different computing units. Simulate the ADC/PWM peripheral/inter-processor communication with plant and deploy to prototype systems.
Perform closed-loop simulations that include the behavior of peripherals such as ADCs and PWMs. Models can account for ADC-PWM synchronization and latency.
Multiprocessor Architecture Modeling
Partition algorithms between multiple processors to achieve design modularity and to improve performance. Model multiprocessor execution and inter-processor data communication.
Deploy to Microcontroller and Microprocessor Boards
Perform rapid prototyping on hardware boards by generating software applications with Embedded Coder. Perform on-device profiling to fine-tune applications.