SoC Blockset


SoC Blockset

Design, analyze, and deploy hardware/software applications for AMD and Intel SoC devices

5G and SDR Applications

With Wireless HDL Toolbox, simulate and deploy a 5G NR MIB recovery algorithm or a 5G NR SIB1 recovery algorithm for FR1 and FR2 using an SoC Blockset implementation. Use Zynq-based radios with Analog Devices RF cards to prototype, verify, and test practical wireless systems.

Vision Applications

Build models using SoC reference designs that enable capturing live video to simulation, processing video streams on hardware, and integration with deep learning processors. Develop prototype designs with live video input using the SoC Blockset hardware support package.

Motor and Power Electronics Controls Applications

Model and simulate motor and power electronics controllers partitioned between processors and programmable logic. Automate C code generation and compilation along with IP core generation to target AMD Zynq and Versal devices as well as Intel SoC FPGAs.

Target Versal Devices

Analyze system designs using predefined models of the latest AMD programmable SoC devices, then use the SoC Builder tool to deploy to development boards for testing.

Target RFSoC Devices

­Simulate and deploy radar applications targeted to AMD RFSoC devices. Deploy 5G signal detection algorithms to RFSoC boards, using SoC Blockset to program the hardware, load test data into memory, and control the deployed design. Implement frequency-hopping algorithms for CDMA and FHSS applications with AMD UltraScale+ RFSoCs.

Target AMD UltraScale+ MPSoC and Zynq-7000 Devices

Develop applications such as motor/power electronics controls or wireless communications for implementation on MPSoC and Zynq-7000 platforms. Use the SoC Builder app to configure, build, and deploy hardware/software algorithms to prototype hardware.

COTS Boards and Custom Board Support

Use the OS Customizer tool to modify and add libraries to the Linux® distribution for your embedded processor. Customize the embedded Linux operating system of supported boards.

Model DDR Memory

­Model DDR memory and simulate shared memory transactions between hardware logic and embedded processors. Configure DMA controllers to arbitrate memory traffic. Account for memory latency and throughput in simulation.

Generate HDL Coder Reference Designs

Generate HDL Coder reference designs directly from SoC Blockset models, then use the HDL Workflow Advisor tool to integrate IP cores created with HDL Coder.

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