SoC Blockset


SoC Blockset

Design, analyze, and deploy hardware/software applications for AMD and Intel SoC devices

Architectures from Specifications

Perform preliminary analysis of your design to determine whether the software tasks in your application can be scheduled on your chosen hardware. Start with a functional architecture of the application in System Composer and allocate functional components to processors or programmable logic.

Target Versal, Zynq RFSoC/MPSoC

Analyze system designs using predefined models of the latest AMD programmable SoC devices, then use the SoC Builder tool to deploy to development boards for testing.

Documentation (Versal, RFSoC/MPSoC)
Examples (Versal, RFSoC/MPSoC)

5G Applications on RFSoC Devices

With Wireless HDL Toolbox, simulate and deploy a 5G NR MIB recovery algorithm or a 5G NR SIB1 recovery algorithm for FR1 and FR2 using an SoC Blockset implementation targeted to AMD Zynq UltraScale+ RFSoC boards.

Analyze Algorithm Resource Usage

Analyze Simulink models or MATLAB algorithms to generate reports summarizing the number of arithmetic operators required for implementation. Use these reports to compare different architectures for FPGA, ASIC, and SoC devices, evaluate design tradeoffs, and explore hardware/software partitioning options.

Model DDR Memory

­Model DDR memory and simulate shared memory transactions between hardware logic and embedded processors. Configure DMA controllers to arbitrate memory traffic. Account for memory latency and throughput in simulation.

Analyze Task Execution

Model task execution of embedded software as managed by the operating system (OS). Simulate tasks with accurate timing, accounting for context switching, task preemption, and execution duration. Model software interrupts generated by FPGA fabric. Apply statistics to simulate nondeterministic task durations or incorporate task durations measured during hardware testing.

Generate HDL Coder Reference Designs

Generate HDL Coder reference designs directly from SoC Blockset models, then use the HDL Workflow Advisor tool to integrate IP cores created with HDL Coder.

Target COTS Boards and Custom Boards

­Use the OS Customizer tool to modify and add libraries to the Linux® distribution for your embedded processor. Customize the embedded Linux operating system of supported boards.

Featured Applications

Evaluate vision, communications, and radar applications while taking into account the effects of processor, FPGA, and DDR memory subsystems. Implement motor and power electronics controllers partitioned between processors and programmable logic.