I want to design a simple digital systen with Simulink in order to:
1. simulate its behaviour with Matlab
2. generate the VHDL code for a FPGA synthesis.
I would use the same system design to simulation and generation but to simulate with Matlab I must stimulate my circuit with input block (in1) using a "double" data type, instead to generate VHDL code I must use in1 with data type "uint8".
a = [0 1 1 1 0 0 0 1 0 1];
in1 = uint8(a);
If I try to simulate on Matlab that code with I have this error :
"Input format not supported. Available formats include: (1) a Simulink.SimulationData.Dataset object, (2) a double non-complex matrix, (3) a structure with or without time, (4) a MATLAB timeseries object, (5) a structure with MATLAB timeseries objects at all leaves (for bus input). All formats require the data to be finite (not Inf or NaN)."
Is it not possible use the same configuration to simuate and generate HDL code?
Could you help me please?