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Bharath Venkataraman


Last seen: 4 days ago

MathWorks

200 total contributions since 2013

Bharath Venkataraman's Badges

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Answered
QPSK Modulation Verilog Code generation error?
It appears that you need to covert the design to use fixed-point as well as set appropriate sample rates for your sources. Pleas...

6 days ago | 0

Answered
I'm getting this error and I'm unable to figure out this. Please help
Please check if you have an HDL simulator that is supported. Here is the list supported by HDL Verifier: https://www.mathworks.c...

25 days ago | 0

Answered
HDL Coder streaming input instead of vector
In this case, you want to use the Unbuffer block to stream the data in sample by sample.

2 months ago | 0

Answered
How do I call an FFT multiple times with HDL Coder: System Object Methods in Loops?
Here is an equivalent Simulink model. Data comes in through the Signal To Workspace blocks whose input can come in from any wor...

4 months ago | 0

Answered
How to configure modelsim in Matlab?
You can specify the vsimdir property value pair via vsimargs to vsimulink. See this page for details. You should also be able t...

8 months ago | 1

Answered
Matlab HDL coder target frequency
The FFT HDL Optimized block & System object allow you to send 2^N samples per clock into the FFT. If you are able to get an FPGA...

9 months ago | 0

Answered
Discrete FIR Filter input port
As you have observed, all the coefficients are to be provided at the input interface. One way to do this would be to take each ...

9 months ago | 0

Answered
'vsim' requires HDL Verifier.
If you are trying to co-simulate MATLAB code and HDL code in ModelSim, you will need the HDL Verifier product to do so.

1 year ago | 1

Answered
LTE HDL MIB Recovery block explanation
The LTE Toolbox example on Cell Search has further information and MATLAB code that you can run. For the HDL implementation, yo...

1 year ago | 0

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Answered
How do I call an FFT multiple times with HDL Coder: System Object Methods in Loops?
As shown in the example, the HDL FFT needs into the separated out into a separte design file. The example puts the HDL-optimized...

1 year ago | 0

Answered
Implementing scanning indow using HDL FIFOs
We have a block that does the windowing - please look at the Line Buffer block. I believe this will meet your needs.

1 year ago | 0

Answered
F-OFDM filtering for 5G
You are right - this is not a formal part of the 5G standard. You can look at this example to see how F-OFDM behaves vs. OFDM. ...

1 year ago | 0

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Answered
how to plot 8 bit data which is receiving from FPGA by UART?
You can display this via the Logic Analyzer or Time Scope.

1 year ago | 0

Answered
Super Sample Rate FIR Resource Utilization
HDL code for the super-sample FIR Filters does optimize for powers of 2, zeros and symmetry. I've attached a simple model which ...

1 year ago | 0

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Answered
Implementation of median filter on FPGA
Are you able to generate VHDL (which is the default), or is there an error during HDL code genration? The last section (Generat...

1 year ago | 0

Answered
Implementation of median filter on FPGA
Here is a link to an example of how to do this in Simulink.

1 year ago | 0

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Answered
converting a vector input to scalar
The Signal From Workspace block should help you get your data into Simulink. https://www.mathworks.com/help/dsp/ref/signalfromw...

1 year ago | 0

Answered
CRC generation in HDL
You can set the CRC polynomial on the block and send in the bits either serially or multiple bits at a time based on your polyno...

1 year ago | 0

Answered
How to speed up a Simulink simulation of slow mechanics requiring a fast clock?
There are a wide variety of things you can do. The first thing to try is to run the model in Accelerator or Rapid Accelerator mo...

2 years ago | 0

Answered
Cosimulation Wizard and required toolboxes
You need the HDL Verifier product to use the Cosimulation Wizard.

2 years ago | 0

Answered
HDL Coder - reducing size of fixed-point variables
The number of bytes taken to store the fixed-point variable in MATLAB does not determine the number of bits in HDL. te number of...

2 years ago | 0

Answered
Generating VHDL code from MATLAB program using HDL generator
Is there a pattern to how x gets its value that you can utilize here? For example, if x is incremented by 1 all the time, or onl...

2 years ago | 0

Answered
"Abnormal exit: Can't find bus object 'pixelcontrol' in the MATLAB workspace" error in HDL Coder
Please try running the command pixelcontrolbus in the MATLAB command line.

2 years ago | 0

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Answered
Why i do not get a fixed point out from a FFT HDL optimized block in simulink?
I may need the model to do further debugging. In the meantime, I created a simple FFT model in R2018b which seems to do the righ...

2 years ago | 1

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Answered
Why i do not get a fixed point out from a FFT HDL optimized block in simulink?
Could you double click on the FFT block and send a snapshot of its parameters?

2 years ago | 0

Answered
HDL Coder doesn't create input for clock signal
Does your MATLAB code have states? You need to have some state in the MATLAB code to have resets and clocks. This is an example...

2 years ago | 0

Answered
What values to use for minimum blancking for a pixel streaming interface
Typical video interfaces (240p and higher resolution) will have sufficient blanking, so one way to go is to pick blanking requir...

2 years ago | 0

Answered
VariableSizeFFTHDLExample File Not found
The LTE HDL Toolbox product is required for this example.

2 years ago | 1

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Answered
How to read an image in a simulink
Please look at the examples in Vision HDL Toolbox to see how to go about doing this. https://www.mathworks.com/help/visionhdl/e...

2 years ago | 0

Answered
使用Generate HDL Code from MATLAB Code Using the Command Line Interface时,显示错误使用 codegen
It appears that you need to set up the path to ISE. See teh function hdlsetuptoolpath for information on how to do this.

2 years ago | 0

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