How to efficiently manage control signals, such as ValidIn or StartIn, for HDL blocks?

In order to handle some of the HDL-ready blocks from Simulink HDL Library, I need to manage control signals, in addition to data streams.

For example ValidIn or StartIn and so on. Same story for output, with ValidOut or EndOut etc...

How can I create and manage these signals with sources and sinks in an efficient way?

I have seen example using Pulse Generator block, but to me it sounds odd. See (https://nl.mathworks.com/help/comm/ug/using-hdl-optimized-crc-library-blocks.html)

Marco

Answer 1

[Bharath Venkataraman]

There are a variety of ways to do this.

1. As you have noted, you can use Simulink block like the pulse generator to drive these signals. Here is a RS Encoder example, FFT Example, FIR example, ATan2 example for this mode of operation.
2. You could construct this in a MATLAB Function block and drive signals from there.
3. You could create all signals (data, validIn, startIn, endIn) in MATLAB as arrays and use the From Workspace block to read them into your simulation. Here is an LDPC Decoder example that shows how to do it this way.
4. If you have access to Wireless HDL Toolbox, there are utilities that help you convert from frame to sample (block, function) and samples back to frames (block, function) that generate the appropriate control signals.

For the output signals:

1. You can log these signals and access the logged signals in MATLAB
2. You could also view them in the Logic Analyzer (as shown in this CRC example)

[Marco]

Amazing answer, really complete. Thank you Bharath!

[Bharath Venkataraman]

You are welcome, @Marco!