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Answered
Getting Error while using HDL Coder
If you are still facing the issue please reach out to MathWorks technical support. I tried the example model in R2025b release ...
Getting Error while using HDL Coder
If you are still facing the issue please reach out to MathWorks technical support. I tried the example model in R2025b release ...
12 hours ago | 0
Answered
Errors when using HDL coder
Can you reach out to technical support with the reproduction steps? Contact Support - MATLAB & Simulink
Errors when using HDL coder
Can you reach out to technical support with the reproduction steps? Contact Support - MATLAB & Simulink
9 days ago | 0
Answered
sampling time mismatch in simulink and harware
You do not have to model at the FPGA clock rate in the Simulink model. There are several strategies possible. HDL Coder Evaluat...
sampling time mismatch in simulink and harware
You do not have to model at the FPGA clock rate in the Simulink model. There are several strategies possible. HDL Coder Evaluat...
11 days ago | 0
Answered
An instance of AMD cannot be generated in the HDL Coder
https://www.mathworks.com/help/hdlcoder/ug/generate-hdl-code-amd-floating-point-library.html If you are using a recent release ...
An instance of AMD cannot be generated in the HDL Coder
https://www.mathworks.com/help/hdlcoder/ug/generate-hdl-code-amd-floating-point-library.html If you are using a recent release ...
12 days ago | 1
| accepted
Answered
How to register a reference design that contains block design, rtl, and xilinx IP core?
HDL Coder has a lot of integration touch points with custom code, custom IP core modules and integrating with Vits Model Compose...
How to register a reference design that contains block design, rtl, and xilinx IP core?
HDL Coder has a lot of integration touch points with custom code, custom IP core modules and integrating with Vits Model Compose...
26 days ago | 0
Answered
generated HDL code failing in cadence AMS
https://www.mathworks.com/help/hdlcoder/index.html HDL Coder generates Synthesizable RTL. For the list of supported...
generated HDL code failing in cadence AMS
https://www.mathworks.com/help/hdlcoder/index.html HDL Coder generates Synthesizable RTL. For the list of supported...
26 days ago | 1
Answered
fixdt outof bounds error for data conversion block
This looks like an unexpected behavior and is a bug in the block implementation. https://www.mathworks.com/help/wireless-hdl/u...
fixdt outof bounds error for data conversion block
This looks like an unexpected behavior and is a bug in the block implementation. https://www.mathworks.com/help/wireless-hdl/u...
26 days ago | 0
Answered
Import VHDL in simulink
importhdl Import Verilog or VHDL code and generate Simulink model https://www.mathworks.com/help/hdlcoder/ref/importhdl.html ...
Import VHDL in simulink
importhdl Import Verilog or VHDL code and generate Simulink model https://www.mathworks.com/help/hdlcoder/ref/importhdl.html ...
1 month ago | 0
Answered
HDL Coder generated Verilog code for 2-D LUT block propogates X in Vivado Simulator
Could you please share your test model along with the version of MATLAB you are using? We tested with R2025b using the atta...
HDL Coder generated Verilog code for 2-D LUT block propogates X in Vivado Simulator
Could you please share your test model along with the version of MATLAB you are using? We tested with R2025b using the atta...
2 months ago | 0
Answered
Sine and Cosine HDL Optimised Block
Please find attached a basic model using the block. https://www.mathworks.com/help/hdlcoder/ref/sinehdloptimizedandcosinehdlopt...
Sine and Cosine HDL Optimised Block
Please find attached a basic model using the block. https://www.mathworks.com/help/hdlcoder/ref/sinehdloptimizedandcosinehdlopt...
2 months ago | 0
Answered
Regarding HDL_Coder license
Please reach out to the tech support and connect with the licensing team.
Regarding HDL_Coder license
Please reach out to the tech support and connect with the licensing team.
2 months ago | 0
Answered
HDL Coder generated Verilog code for 2-D LUT block propogates X in Vivado Simulator
Could you please share the sample model? The input types and block parameters are essential for generating HDL code. Addition...
HDL Coder generated Verilog code for 2-D LUT block propogates X in Vivado Simulator
Could you please share the sample model? The input types and block parameters are essential for generating HDL code. Addition...
3 months ago | 0
Answered
Error in Setup for HDL Coder Support Package for AMD FPGA and SoC Devices
What version of MATLAB are you using? Have you reached out to tech support?
Error in Setup for HDL Coder Support Package for AMD FPGA and SoC Devices
What version of MATLAB are you using? Have you reached out to tech support?
3 months ago | 0
Answered
Why am I getting the error "found unsupported dynamic matrix type" in HDL Coder R2024b?
Related Thread https://www.mathworks.com/matlabcentral/answers/2179433-why-does-hdl-code-generation-give-errors-when-variable-s...
Why am I getting the error "found unsupported dynamic matrix type" in HDL Coder R2024b?
Related Thread https://www.mathworks.com/matlabcentral/answers/2179433-why-does-hdl-code-generation-give-errors-when-variable-s...
3 months ago | 0
Answered
Discrepancy between Simulink and hdl code behaviour
Could you reach out to tech support for assistance, or alternatively, share your model here? We’d be happy to take a look and pr...
Discrepancy between Simulink and hdl code behaviour
Could you reach out to tech support for assistance, or alternatively, share your model here? We’d be happy to take a look and pr...
4 months ago | 0
Answered
i want to implement 5G NR OFDM system in verilog code using HDL coder
https://www.mathworks.com/help/soc/ug/5g-nr-intro-downlink-signal-detection-rfsoc.html This example shows how to deploy a 5G ...
i want to implement 5G NR OFDM system in verilog code using HDL coder
https://www.mathworks.com/help/soc/ug/5g-nr-intro-downlink-signal-detection-rfsoc.html This example shows how to deploy a 5G ...
5 months ago | 0
Answered
Does SoC Builder do build optimizations, can I see the resources mapping and can I change it?
For working with the AMD Zynq UltraScale+ RFSoC ZCU111 Evaluation Board using HDL Coder, MathWorks provides detailed documentati...
Does SoC Builder do build optimizations, can I see the resources mapping and can I change it?
For working with the AMD Zynq UltraScale+ RFSoC ZCU111 Evaluation Board using HDL Coder, MathWorks provides detailed documentati...
6 months ago | 1
Answered
Interface with the Deep Learning Processor IP Core (Execution Modes)
System Integration of Deep Learning Processor IP Core This page shows lists the relevant examples https://www.mathworks.com/h...
Interface with the Deep Learning Processor IP Core (Execution Modes)
System Integration of Deep Learning Processor IP Core This page shows lists the relevant examples https://www.mathworks.com/h...
6 months ago | 0
| accepted
Answered
Unable to set Synthesis Attribute on Entity using hdlset_param
In the latest release you should see Block and Block Outputs (Signal) related synthesis attributes specification dialogs and t...
Unable to set Synthesis Attribute on Entity using hdlset_param
In the latest release you should see Block and Block Outputs (Signal) related synthesis attributes specification dialogs and t...
6 months ago | 0
Answered
Unable to set Synthesis Attribute on Entity using hdlset_param
https://www.mathworks.com/help/hdlcoder/ug/configure-custom-synthesis-attributes-for-simulink-blocks.html HDL Coder allows at...
Unable to set Synthesis Attribute on Entity using hdlset_param
https://www.mathworks.com/help/hdlcoder/ug/configure-custom-synthesis-attributes-for-simulink-blocks.html HDL Coder allows at...
6 months ago | 0
Answered
Deep Learning HDL Toolbox with CycloneV SoC board
Can you consider using the example and extend to DE-10 Nao Kit? https://www.mathworks.com/help/hdlcoder/ug/define-and-register-...
Deep Learning HDL Toolbox with CycloneV SoC board
Can you consider using the example and extend to DE-10 Nao Kit? https://www.mathworks.com/help/hdlcoder/ug/define-and-register-...
6 months ago | 0
Answered
Convert a part of simulink model of my project to VHDL or Verilog code for FPGA
https://www.mathworks.com/help/hdlcoder/simscape-to-hdl.html Simscape Hardware-in-the-Loop Workflow Generate HDL code from S...
Convert a part of simulink model of my project to VHDL or Verilog code for FPGA
https://www.mathworks.com/help/hdlcoder/simscape-to-hdl.html Simscape Hardware-in-the-Loop Workflow Generate HDL code from S...
8 months ago | 0
Answered
Is it possible to change Simulink MATLAB Function Block 1-indexing to 0-indexing?
If possible can you share your model and the version of MATLAB you are using? There are few tricks in MATLAB coding and design...
Is it possible to change Simulink MATLAB Function Block 1-indexing to 0-indexing?
If possible can you share your model and the version of MATLAB you are using? There are few tricks in MATLAB coding and design...
9 months ago | 0
| accepted
Answered
Dose HDL coder generate Verilog HDL-1995 verision or Verilog HDL-2001 version？
HDL Coder Language Support VHDL, Verilog, and SystemC HLS Language Support The generated HDL code complies with the following...
Dose HDL coder generate Verilog HDL-1995 verision or Verilog HDL-2001 version？
HDL Coder Language Support VHDL, Verilog, and SystemC HLS Language Support The generated HDL code complies with the following...
9 months ago | 1
Answered
When I click on "View Code" after generating Verilog code in HDL Coder, the program doesn't respond.
https://www.mathworks.com/help/hdlcoder/ug/traceability-report.html If you are facing issues with code view please reach out to...
When I click on "View Code" after generating Verilog code in HDL Coder, the program doesn't respond.
https://www.mathworks.com/help/hdlcoder/ug/traceability-report.html If you are facing issues with code view please reach out to...
9 months ago | 0
| accepted
Answered
HDL Code Generation Issue – Exceeding IO Pin Count Threshold & MATLAB Freezing
If the generated HDL DUT code results in unreasonable IO, it may eventually lead to failure to meet pin constraint during synthe...
HDL Code Generation Issue – Exceeding IO Pin Count Threshold & MATLAB Freezing
If the generated HDL DUT code results in unreasonable IO, it may eventually lead to failure to meet pin constraint during synthe...
9 months ago | 0
Answered
SigmoidLayer wont work while implementing on ZC706
Thank you for reporting this. Development team is able to reproduce the issue and will post an update soon.
SigmoidLayer wont work while implementing on ZC706
Thank you for reporting this. Development team is able to reproduce the issue and will post an update soon.
9 months ago | 0
Answered
Simulink HDL Coder error when generating
This is an unexpected error handling the if/elseif control structure. Please reach to tech support or share your model here. We ...
Simulink HDL Coder error when generating
This is an unexpected error handling the if/elseif control structure. Please reach to tech support or share your model here. We ...
10 months ago | 0
Answered
How can we tune the Discrete integrator of the HDL Coder for second order generalized integrator for FPGA
Can you share the model here or via tech support? Thanks
How can we tune the Discrete integrator of the HDL Coder for second order generalized integrator for FPGA
Can you share the model here or via tech support? Thanks
10 months ago | 0
| accepted
Answered
Can't register a custom board for the HDL Deep Learning Toolbox
>> Does MATLAB have the option to register a custom board? Yes, You can see the doc here https://www.mathworks.com/help/hdlcode...
Can't register a custom board for the HDL Deep Learning Toolbox
>> Does MATLAB have the option to register a custom board? Yes, You can see the doc here https://www.mathworks.com/help/hdlcode...
10 months ago | 0
