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Answered
how to deal with stream data to HDLFFT?
Implement FFT Algorithm for FPGA HDL Coder, DSP HDL Toolbox, Simulink This example shows how to implement a hardware-targeted ...
how to deal with stream data to HDLFFT?
Implement FFT Algorithm for FPGA HDL Coder, DSP HDL Toolbox, Simulink This example shows how to implement a hardware-targeted ...
1 day ago | 0
Answered
HDL QPSK Transmitter and Receiver example problem
Please reach out to tech support if it is still reproducible. Here is the generated output for the example. >> makehdl('commhdl...
HDL QPSK Transmitter and Receiver example problem
Please reach out to tech support if it is still reproducible. Here is the generated output for the example. >> makehdl('commhdl...
1 day ago | 0
Answered
matlab to vhdl conversion
You should consider using MATLAB Copilot to translate your MATLAB to follow Synthesis friendly rules. Here is some guidance to...
matlab to vhdl conversion
You should consider using MATLAB Copilot to translate your MATLAB to follow Synthesis friendly rules. Here is some guidance to...
1 day ago | 0
Answered
Build Linux Image for HDL Coder
Build Custom Linux Image for HDL Coder IP Core https://www.mathworks.com/help/hdlcoder/ug/xilinx-zynq-linux-image-for-custom-bo...
Build Linux Image for HDL Coder
Build Custom Linux Image for HDL Coder IP Core https://www.mathworks.com/help/hdlcoder/ug/xilinx-zynq-linux-image-for-custom-bo...
3 days ago | 0
| accepted
Answered
CIC Filter
These two blocks support HDL Code Generation CIC Decimator https://www.mathworks.com/help/dsphdl/ref/cicdecimator.html https:...
CIC Filter
These two blocks support HDL Code Generation CIC Decimator https://www.mathworks.com/help/dsphdl/ref/cicdecimator.html https:...
3 days ago | 0
Answered
I want to generate HDL from a System Object that contains several dsp.FIRFilter objects, the number of which is determined by a Nontunable property
You are correct. HDL Coder (and hardware modeling in general) does not support dynamic behavior in MATLAB code. All structural...
I want to generate HDL from a System Object that contains several dsp.FIRFilter objects, the number of which is determined by a Nontunable property
You are correct. HDL Coder (and hardware modeling in general) does not support dynamic behavior in MATLAB code. All structural...
5 days ago | 0
Answered
HDL Code Generation for Moving Maximum function
HDL Coder does not support Moving Maximum block in DSP System Toolbox out of the box. Consider using the attached model built us...
HDL Code Generation for Moving Maximum function
HDL Coder does not support Moving Maximum block in DSP System Toolbox out of the box. Consider using the attached model built us...
6 days ago | 0
Question
HDL Code Generation for Moving Maximum function
How do I generate HDL Code from Moving Maximum block in DSP System Toolbox?
6 days ago | 1 answer | 0
1
answerAnswered
Delay balancing failed when generating HDL code
It looks like you are hitting a delay balancing error due to latency in a feedback look in the model cannot be matched. https...
Delay balancing failed when generating HDL code
It looks like you are hitting a delay balancing error due to latency in a feedback look in the model cannot be matched. https...
9 days ago | 0
Answered
simulink can't map matrie to RAM
Hi, Can you please share the model here or reach out to technical support for additional guidance? Thanks
simulink can't map matrie to RAM
Hi, Can you please share the model here or reach out to technical support for additional guidance? Thanks
12 days ago | 0
Answered
Getting Error while using HDL Coder
If you are still facing the issue please reach out to MathWorks technical support. I tried the example model in R2025b release ...
Getting Error while using HDL Coder
If you are still facing the issue please reach out to MathWorks technical support. I tried the example model in R2025b release ...
21 days ago | 0
Answered
Errors when using HDL coder
Can you reach out to technical support with the reproduction steps? Contact Support - MATLAB & Simulink
Errors when using HDL coder
Can you reach out to technical support with the reproduction steps? Contact Support - MATLAB & Simulink
29 days ago | 0
Answered
sampling time mismatch in simulink and harware
You do not have to model at the FPGA clock rate in the Simulink model. There are several strategies possible. HDL Coder Evaluat...
sampling time mismatch in simulink and harware
You do not have to model at the FPGA clock rate in the Simulink model. There are several strategies possible. HDL Coder Evaluat...
1 month ago | 0
Answered
An instance of AMD cannot be generated in the HDL Coder
https://www.mathworks.com/help/hdlcoder/ug/generate-hdl-code-amd-floating-point-library.html If you are using a recent release ...
An instance of AMD cannot be generated in the HDL Coder
https://www.mathworks.com/help/hdlcoder/ug/generate-hdl-code-amd-floating-point-library.html If you are using a recent release ...
1 month ago | 1
| accepted
Answered
How to register a reference design that contains block design, rtl, and xilinx IP core?
HDL Coder has a lot of integration touch points with custom code, custom IP core modules and integrating with Vits Model Compose...
How to register a reference design that contains block design, rtl, and xilinx IP core?
HDL Coder has a lot of integration touch points with custom code, custom IP core modules and integrating with Vits Model Compose...
2 months ago | 0
Answered
generated HDL code failing in cadence AMS
https://www.mathworks.com/help/hdlcoder/index.html HDL Coder generates Synthesizable RTL. For the list of supported...
generated HDL code failing in cadence AMS
https://www.mathworks.com/help/hdlcoder/index.html HDL Coder generates Synthesizable RTL. For the list of supported...
2 months ago | 1
Answered
fixdt outof bounds error for data conversion block
This looks like an unexpected behavior and is a bug in the block implementation. https://www.mathworks.com/help/wireless-hdl/u...
fixdt outof bounds error for data conversion block
This looks like an unexpected behavior and is a bug in the block implementation. https://www.mathworks.com/help/wireless-hdl/u...
2 months ago | 0
Answered
Import VHDL in simulink
importhdl Import Verilog or VHDL code and generate Simulink model https://www.mathworks.com/help/hdlcoder/ref/importhdl.html ...
Import VHDL in simulink
importhdl Import Verilog or VHDL code and generate Simulink model https://www.mathworks.com/help/hdlcoder/ref/importhdl.html ...
2 months ago | 0
Answered
HDL Coder generated Verilog code for 2-D LUT block propogates X in Vivado Simulator
Could you please share your test model along with the version of MATLAB you are using? We tested with R2025b using the atta...
HDL Coder generated Verilog code for 2-D LUT block propogates X in Vivado Simulator
Could you please share your test model along with the version of MATLAB you are using? We tested with R2025b using the atta...
2 months ago | 0
Answered
Sine and Cosine HDL Optimised Block
Please find attached a basic model using the block. https://www.mathworks.com/help/hdlcoder/ref/sinehdloptimizedandcosinehdlopt...
Sine and Cosine HDL Optimised Block
Please find attached a basic model using the block. https://www.mathworks.com/help/hdlcoder/ref/sinehdloptimizedandcosinehdlopt...
3 months ago | 0
Answered
Regarding HDL_Coder license
Please reach out to the tech support and connect with the licensing team.
Regarding HDL_Coder license
Please reach out to the tech support and connect with the licensing team.
3 months ago | 0
Answered
HDL Coder generated Verilog code for 2-D LUT block propogates X in Vivado Simulator
Could you please share the sample model? The input types and block parameters are essential for generating HDL code. Addition...
HDL Coder generated Verilog code for 2-D LUT block propogates X in Vivado Simulator
Could you please share the sample model? The input types and block parameters are essential for generating HDL code. Addition...
3 months ago | 0
Answered
Error in Setup for HDL Coder Support Package for AMD FPGA and SoC Devices
What version of MATLAB are you using? Have you reached out to tech support?
Error in Setup for HDL Coder Support Package for AMD FPGA and SoC Devices
What version of MATLAB are you using? Have you reached out to tech support?
4 months ago | 0
Answered
Why am I getting the error "found unsupported dynamic matrix type" in HDL Coder R2024b?
Related Thread https://www.mathworks.com/matlabcentral/answers/2179433-why-does-hdl-code-generation-give-errors-when-variable-s...
Why am I getting the error "found unsupported dynamic matrix type" in HDL Coder R2024b?
Related Thread https://www.mathworks.com/matlabcentral/answers/2179433-why-does-hdl-code-generation-give-errors-when-variable-s...
4 months ago | 0
Answered
Discrepancy between Simulink and hdl code behaviour
Could you reach out to tech support for assistance, or alternatively, share your model here? We’d be happy to take a look and pr...
Discrepancy between Simulink and hdl code behaviour
Could you reach out to tech support for assistance, or alternatively, share your model here? We’d be happy to take a look and pr...
5 months ago | 0
Answered
i want to implement 5G NR OFDM system in verilog code using HDL coder
https://www.mathworks.com/help/soc/ug/5g-nr-intro-downlink-signal-detection-rfsoc.html This example shows how to deploy a 5G ...
i want to implement 5G NR OFDM system in verilog code using HDL coder
https://www.mathworks.com/help/soc/ug/5g-nr-intro-downlink-signal-detection-rfsoc.html This example shows how to deploy a 5G ...
5 months ago | 0
Answered
Does SoC Builder do build optimizations, can I see the resources mapping and can I change it?
For working with the AMD Zynq UltraScale+ RFSoC ZCU111 Evaluation Board using HDL Coder, MathWorks provides detailed documentati...
Does SoC Builder do build optimizations, can I see the resources mapping and can I change it?
For working with the AMD Zynq UltraScale+ RFSoC ZCU111 Evaluation Board using HDL Coder, MathWorks provides detailed documentati...
6 months ago | 1
Answered
Interface with the Deep Learning Processor IP Core (Execution Modes)
System Integration of Deep Learning Processor IP Core This page shows lists the relevant examples https://www.mathworks.com/h...
Interface with the Deep Learning Processor IP Core (Execution Modes)
System Integration of Deep Learning Processor IP Core This page shows lists the relevant examples https://www.mathworks.com/h...
6 months ago | 0
| accepted
Answered
Unable to set Synthesis Attribute on Entity using hdlset_param
In the latest release you should see Block and Block Outputs (Signal) related synthesis attributes specification dialogs and t...
Unable to set Synthesis Attribute on Entity using hdlset_param
In the latest release you should see Block and Block Outputs (Signal) related synthesis attributes specification dialogs and t...
7 months ago | 0
Answered
Unable to set Synthesis Attribute on Entity using hdlset_param
https://www.mathworks.com/help/hdlcoder/ug/configure-custom-synthesis-attributes-for-simulink-blocks.html HDL Coder allows at...
Unable to set Synthesis Attribute on Entity using hdlset_param
https://www.mathworks.com/help/hdlcoder/ug/configure-custom-synthesis-attributes-for-simulink-blocks.html HDL Coder allows at...
7 months ago | 0
