Hardware Implementation Pane

Hardware Implementation Pane Overview

Hardware board settings

Set the processing unit for the MCU current model.

Parameter	Description	Default Value
Processing Unit	Select processing unit for SoC model deployment.	None

Task profiling in simulation

Define the settings to display and record tasks in simulation.

Parameter	Description	Default Value
Show in SDI	Show the task execution data collected in simulation in the Simulation Data Inspector application.	on
Save to file	Save the task execution data to a file.	on
Overwrite file	Overwrite the last task execution data file.	off

Task profiling on processor

Define the settings to display and record tasks on hardware board.

Parameter	Description	Default Value
Show in SDI	Show the task execution data collected on hardware in the Simulation Data Inspector application.	off
Save to file	Save the task execution data to a file.	off
Overwrite file	Overwrite the last task execution data file.	off
Instrumentation	Choose to perform code instrumentation or Kernel instrumentation.	Code
Profiling duration	Choose whether to perform Kernel profiling for an unlimited or limited time duration.	Unlimited

Operating system/scheduler

Define the kernel latency of the OS in simulation of a task.

Parameter	Description	Default Value
Operating system	Specify the operation system.	Linux

Simulation settings

Define the settings used to simulate task execution timing.

Parameter	Description	Default Value
Set random number generator seed	Set the random number generator seed.	off
Seed Value	Specify the seed value for the simulation of task duration deviation.	default
Cache input data at task start	Cache the input data at the start of a task.	off
Kernel latency	Set the simulated delay.	0
Project folder	Specify the project folder.	soc_prj

Board parameters

Define the board parameters.

Parameter	Description	Default Value
Device Address	Network address of hardware board or device.	192.168.1.10
Username	Login username on hardware board or device.	root
Password	Login password on hardware board or device.	root

Processor

Specify processor features for the entire model.

Parameter	Description	Default Value
Number of cores	Set the number of CPU cores in the processor.	1

Build options

Define how SoC builder tool responds when you press Ctrl+B to build your model.

Parameter	Description	Default Value
Build Action	Defines how SoC Builder tool responds when you build your model.	Build, load, and run

Clocking

Define the settings for the clock signals on the embedded processor.

Parameter	Description	Default Value
CPU Clock (MHz)	The CPU clock frequency in MHz.	1000

External mode

Define the external mode communication properties of a model.

Parameter	Description	Default Value
Communication Interface	Transport layer used to exchange data between the development computer and hardware.	TCP/IP
Run external mode in a background thread	Execute the external mode engine in the generated code in a background task.	disabled
Port	IP address port on hardware board.	17725
Verbose	Enable view of the external mode execution progress and updates in the Diagnostic Viewer.	disabled

FPGA design (top-level)

Define the FPGA design parameters for the entire model.

Parameter	Description	Default Value
Include AXI Manager IP for host-based interaction	Use host-based scripts with an integrated JTAG manager on the target platform.	on
Include processing system	For processor-based platforms, include the processing system.	on
Register configuration clock frequency (MHz)	The system configuration clock drives the configuration register interfaces for the vendor IP cores in the system.	50
IP core clock frequency (MHz)	The clock for all Simulink® based generated HDL IP cores.	100

FPGA design (PS mem controllers)

Define the FPGA design parameters for the PS memory controllers. The default values for these parameters vary by board.

Parameter	Description	Default Value
Controller clock frequency (MHz)	Frequency of datapath between PS memory interconnect and PS memory controller.	200
Controller data width (bits)	Bit width of datapath between PS memory interconnect and PS memory controller.	64
Bandwidth derating (%)	For every 100 clocks, will hold off all transaction execution for this number of clocks.	2.3
First write transfer latency (clocks)	Number of clock cycles between write request and start of transfer.	5
Last write transfer latency (clocks)	Number of clock cycles between the end of write transfer and completion of transaction.	5
First read transfer latency (clocks)	Number of clock cycles between read request and start of transfer.	5
Last read transfer latency (clocks)	Number of clock cycles between the end of read transfer and completion of transaction.	5

FPGA design (PL mem controllers)

Define the FPGA design parameters for the PL memory controllers. The default values for these parameters vary by board.

Parameter	Description	Default Value
Controller clock frequency (MHz)	Frequency of datapath between PL memory interconnect and PL memory controller.	200
Controller data width (bits)	Bit width of datapath between PL memory interconnect and PL memory controller.	64
Bandwidth derating (%)	For every 100 clocks, will hold off all transaction execution for this number of clocks.	2.3
First write transfer latency (clocks)	Number of clock cycles between write request and start of transfer.	5
Last write transfer latency (clocks)	Number of clock cycles between the end of write transfer and completion of transaction.	5
First read transfer latency (clocks)	Number of clock cycles between read request and start of transfer.	5
Last read transfer latency (clocks)	Number of clock cycles between the end of read transfer and completion of transaction.	5

FPGA design (mem channels)

Define the FPGA design parameters for the memory channels.

Parameter	Description	Default Value
Interconnect clock frequency (MHz)	Frequency of the master datapath to the interconnect controller in MHz.	200
Interconnect data width (bits)	Data width of master datapath to interconnect controller in bits.	64
Interconnect FIFO depth (num bursts)	Maximum number of bursts that can be buffered before data is dropped.	12
Interconnect almost-full depth	When the almost full depth is reached, the attached channel protocol interface block asserts back pressure to the data source.	8

FPGA design (debug)

Define the FPGA design parameters for debugging.

Parameter	Description	Default Value
Include AXI interconnect monitor	Gather performance metrics of the memory interconnect such as data throughput, latency, and number of bursts executed.	off
Trace capture depth	Maximum number of Trace entries to be logged in trace mode	1024