Controller clock frequency (MHz)

Frequency of datapath between memory interconnect and memory controller

Model Configuration Pane: Target hardware resources / FPGA design (PS mem controllers)

Description

Frequency of datapath between memory interconnect and memory controller.

The clock rate used to drive transactions to the external memory. The controller clock frequency determines the overall system bandwidth for external memory that must be shared among all the masters in the model.

Settings

200 (default)

Default: 200

The default value for this parameter varies as per the selected hardware board.

Programmatic Use

Parameter:

Type:

Values: 200

Default: 200

Version History

Introduced in R2019a