Basics of Test Generation

Create test cases to validate model behavior

Simulink® Design Verifier™ is a powerful tool that enables you to enhance the reliability and robustness of the Simulink models through automated test generation. The Generate Tests feature facilitates the creation of comprehensive test cases that aim to uncover design errors, validate model behavior, and ensure coverage of all functional requirements. By leveraging formal methods, Simulink Design Verifier systematically explores the model's state space to identify critical test scenarios, thus reducing manual testing efforts and accelerating the verification process. You can follow the fundamental steps described, to effectively generate and utilize test cases, ensuring your model meets its specified design criteria and operates as intended.

Blocks

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Test ConditionConstrain signal values in test cases
Test ObjectiveDefine custom objectives that signals must satisfy in test cases
DetectorDetect true duration on input and construct output true duration based on output type
ExtenderExtend true duration of input
ImpliesSpecify condition that produces a certain response
Within ImpliesVerify response occurs within desired duration
Verification SubsystemSpecify proof or test objectives without impacting simulation results or generated code

Functions

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sldvoptionsCreate design verification options object
sldv.conditionTest condition function for Stateflow charts and MATLAB Function blocks
sldv.testTest objective function for Stateflow charts and MATLAB Function blocks
sldvextractExtract subsystem or subchart contents into new model for analysis
sldvtimerIdentify, change, and display timer optimizations
sldvoptionsCreate design verification options object
sldvrunAnalyze model
sldvlogsignalsLog simulation input port values
sldvgencovAnalyze models to obtain missing model coverage
sldvgenspreadsheetGenerate spreadsheet containing test cases (Since R2022b)
sldvruntestSimulate model by using input data
sldvruntestoptsGenerate simulation or execution options for sldvruntest or sldvruncgvtest
sldvharnessoptsDefault options for sldvmakeharness
sldvmakefilterGenerate filter file containing justification rules for objectives with Unsatisfiable, Dead Logic, Falsified, Falsified - No Counterexample, or Error - Needs Simulation status in sldvData file (Since R2022a)
sldvmakeharnessGenerate harness model
sldvmergeharnessMerge test cases and initializations into one harness model
sldvreportGenerate Simulink Design Verifier report
sldvchecksumReturns checksum of model (Since R2021a)

Topics