Tests for Subsystems and Referenced Models
Simulink® Design Verifier™ allows you to generate test cases specifically for individual subsystems and referenced models within a larger Simulink model. This targeted testing approach enables you to isolate and verify the behavior of specific components.
By focusing on subsystems and referenced models, you can:
Perform model level verification early in the development cycle.
Detect and resolve issues in isolated subsystems before system integration.
Test inputs that generates for subsystems can be aggregated to coverage achieved in integration.
Topics
- What Is Component Verification?
An overview of the two approaches to component verification.
- Generate Test Cases for a Subsystem
Analyze an individual subsystem.
- Generate Test Cases for a Reusable Library Subsystem
Analyze a reusable library subsystem.
- Achieve Missing Coverage in Subsystems and Model Blocks
Explains how to convert subsystems to Model blocks before attempting to achieve missing coverage.
- Use Test Generation Advisor to Identify Analyzable Components
Use the Test Generation Advisor to guide model and component analysis.
- Using Existing Coverage Data During Subsystem Analysis
This example shows how Simulink® Design Verifier™ can target its analysis to a single subsystem within a continuous-time closed-loop simulation and generate test cases for missing coverage in that subsystem.
- Analyze a Stateflow Atomic Subchart
Analyze an atomic subchart by using Simulink Design Verifier.
- Use Observer Reference Block for Test Case Generation
Generate test cases using Observer Reference blocks.
