Basics of Test Generation

Create test cases to validate model behavior

Simulink^® Design Verifier™ is a powerful tool that enables you to enhance the reliability and robustness of the Simulink models through automated test generation. The Generate Tests feature facilitates the creation of comprehensive test cases that aim to uncover design errors, validate model behavior, and ensure coverage of all functional requirements. By leveraging formal methods, Simulink Design Verifier systematically explores the model's state space to identify critical test scenarios, thus reducing manual testing efforts and accelerating the verification process. You can follow the fundamental steps described, to effectively generate and utilize test cases, ensuring your model meets its specified design criteria and operates as intended.

Blocks

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Blocks used in Test Generation

Test Condition	Constrain signal values in test cases
Test Objective	Define custom objectives that signals must satisfy in test cases
Detector	Detect true duration on input and construct output true duration based on output type
Extender	Extend true duration of input
Implies	Specify condition that produces a certain response
Within Implies	Verify response occurs within desired duration
Verification Subsystem	Specify proof or test objectives without impacting simulation results or generated code

Functions

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Functions Used in Test Generation

`sldvoptions`	Create Simulink Design Verifier options object
`sldv.condition`	Test condition function for Stateflow charts and MATLAB Function blocks
`sldv.test`	Test objective function for Stateflow charts and MATLAB Function blocks
`sldvextract`	Extract subsystem or subchart contents into new model for analysis
`sldvtimer`	Identify, change, and display timer optimizations
`sldvoptions`	Create Simulink Design Verifier options object
`sldvrun`	Analyze model
`sldvlogsignals`	Log simulation input port values
`sldvgencov`	Analyze models to obtain missing model coverage
`sldvgenspreadsheet`	Generate spreadsheet containing test cases (Since R2022b)
`sldvruntest`	Simulate model by using input data
`sldvruntestopts`	Generate simulation or execution options for `sldvruntest` or `sldvruncgvtest`
`sldvharnessopts`	Default options for `sldvmakeharness`
`sldvmakefilter`	Generate filter file containing justification rules for objectives with `Unsatisfiable`, `Dead Logic`, `Falsified`, `Falsified - No Counterexample`, or `Error - Needs Simulation` status in `sldvData` file (Since R2022a)
`sldvmakeharness`	Generate harness model
`sldvmergeharness`	Merge test cases and initializations into one harness model
`sldvreport`	Generate Simulink Design Verifier report
`sldvchecksum`	Returns checksum of model

Topics

Workflow for Test Generation
Brief overview of test case generation with Simulink Design Verifier.
Check Model Compatibility for Analysis
Check whether your model is compatible with Simulink Design Verifier.
Test Generation Examples
A set of concept examples that illustrates test generation capabilities.
Creating and Executing Test Cases
This example shows how to use Simulink® Design Verifier™ functions to log input signals, create a harness model, generate test cases for missing coverage, merge harness models, and execute test cases.
Test Objective Block
This example shows the use of two custom Test Objective blocks.
Test Condition Block
This example shows how to constrain input values.