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Michael Felger


Last seen: 4 months ago
10 total contributions since 2019

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Question


HDL Coder reset - asynchronous and synchronous possible?
Hi, is it possible to generate HDL code with both, asynchronous and synchronous reset? https://de.mathworks.com/help/hdlfilter...

1 year ago | 1 answer | 0

1

answer

Question


stateflow hdl code generation hierachy flatten
Hi, I use stateflow for HDL-Code generation of an fsm. The stateflow has several hierachies. The hierachies are mainly for rea...

1 year ago | 1 answer | 0

1

answer

Question


HDL Coder custom file header - settings
Hi, generating VHDL-Code with HDL coder, there are some informations (like filename, date, module) in the default header. It ...

1 year ago | 1 answer | 0

1

answer

Question


HDL Coder to / downto order
Hi, I'm using HDL Coder to generade VHDL code for a simulink block. In the entity, the port order is generated as follow: for...

1 year ago | 1 answer | 0

1

answer

Answered
How do you generate a registered output from Stateflow?
I have exactly the same question!

1 year ago | 0

Question


HDL Coder 'abs' : Double and complex data types not supported.
I'm using a simulink model to generate HDL code for simulation, with double values. The error is clear, as "Double and complex ...

1 year ago | 1 answer | 0

1

answer

Question


stateflow variant states possible?
Is is possible to add variants of a state inside a stateflow diagram, similar to variant subsystems in simulink?

1 year ago | 3 answers | 1

3

answers

Question


Why don't i get a data type mismatch error?
Hi, following is inside my simulink model: a Stateflow chart, inside this chart: a 2-dimensional array a(5,5), data type...

2 years ago | 0 answers | 0

0

answers

Question


HDL Coder disable Clock Enable output port
How can I disable the Clock Enable output port in generated VDHL-Code? I can specify the name In HDL Code Generation -> Global ...

2 years ago | 2 answers | 0

2

answers

Question


How do I display logged local data of stateflow in Logic Analyzer
I would like to log a Local variable in a stateflow diagram and view it in the Logic Analyzer together with other signals. I've...

2 years ago | 1 answer | 0

1

answer