How do you generate a registered output from Stateflow?

If I have an output from a Stateflow diagram; in the generated HDL code the output is assigned from the next state decision logic (combinatorial) _next signal and not from the clocked process, _reg signal. As best practice is to have all outputs from a module being registered a unit delay is added to the output external to the stateflow. However when the generated code is synthesised this register is identified as an equivalent register to the equivalent _reg signal and removed, generating a warning.

How do I generate an output from stateflow that is sourced from the _reg signal as opposed to the the _next signal so that I do not need to put unit delays external to the stateflow diagram?

Answer 1

[Michael Felger]

I have exactly the same question!

[James Price]

Hi Michael, the solution I have employed is that when creating my Stateflow diagrams I have two super states with the execution order set as parallel (and). I then use the priority 1 super state to contain purely assignments from internal registers to outputs - having these as priority 1 means that assignments are generated at the top of the code (i.e. no variables). Superstate 2 is then used to comprise the stateflow diagram required to model the behaviour you require.

Hop this helps.

Answer 2

[Michael Felger]

Update: starting with R2022b, the ClockDrivenOutput parameter for stateflow is available for Moore charts.

https://de.mathworks.com/help/hdlcoder/ug/guidelines-for-hdl-code-generation-using-stateflow-charts.html

With this, registered output is generated.