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HDL Coder to / downto order

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I'm using HDL Coder to generade VHDL code for a simulink block.
In the entity, the port order is generated as follow:
  • for fixed-point variables, the output port is std_logic_vector(n downto 0)
  • for boolean vector (Simulink Port dimension: [1 n]), the output port is std_logic_vector(0 to n)
Is it possible to change the order (to / downto), that all output ports have the same direction, and are not mixed for one entity?
My goal is to have downto for all outputs.

Accepted Answer

Kiran Kintali
Kiran Kintali on 14 Nov 2019
This is a limitation due to an early decision made to emit vector of boolean to use 'TO' syntax and is not currently customizable.
A potential workaround is to concatenate boolean vector to a single signal of ufixN type using BitConcat block and seperating input scalar signal inside DUT back to vector of boolean using BitSlice blocks.

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