I'm using HDL Coder to generade VHDL code for a simulink block.
In the entity, the port order is generated as follow:
- for fixed-point variables, the output port is std_logic_vector(n downto 0)
- for boolean vector (Simulink Port dimension: [1 n]), the output port is std_logic_vector(0 to n)
Is it possible to change the order (to / downto), that all output ports have the same direction, and are not mixed for one entity?
My goal is to have downto for all outputs.