I use stateflow for HDL-Code generation of an fsm.
The stateflow has several hierachies. The hierachies are mainly for readability (grouping the large fsm into subblocks).
This leads to several hierachies in the generated HDL code, which produces deep logical paths in synthesis / hardware implementation.
For example, the generated vhdl-code looks like this:
CASE is_fsm IS
WHEN IN_state1 =>
CASE is_substate IS
WHEN IN_substate_state1 =>
Is it possible to reduce the hierachy of the stateflow diagram when generating VHDL-Code, to reduce the depth of the logical paths in hardware implementation?