Answered

Estimating the latency of a custom IP block in HDL Coder

One of the ways to do this is by having the computatiobn block emit a valid output signal. based on this signal, the controller ...

Estimating the latency of a custom IP block in HDL Coder

One of the ways to do this is by having the computatiobn block emit a valid output signal. based on this signal, the controller ...

9 months ago | 0

Answered

HDL Coder VHDL Output

fix14 implies that there are 14 bits in total. u implies unsigned. En15 indicates that the LSB has a value of 2^-15, with an in...

HDL Coder VHDL Output

fix14 implies that there are 14 bits in total. u implies unsigned. En15 indicates that the LSB has a value of 2^-15, with an in...

9 months ago | 0

Answered

How to profile an HDL Subsystem?

If you synthesize your HDL design in the appropriate HDL tool (example: Vivado), you will know what clock speed you can run the ...

How to profile an HDL Subsystem?

If you synthesize your HDL design in the appropriate HDL tool (example: Vivado), you will know what clock speed you can run the ...

9 months ago | 0

| accepted

Answered

how to generate sine wave for fpga?

You can use the self-guided tutorial on HDL Coder to see how to use the tool. The HDL Optimized NCO block in Simulink will allow...

how to generate sine wave for fpga?

You can use the self-guided tutorial on HDL Coder to see how to use the tool. The HDL Optimized NCO block in Simulink will allow...

9 months ago | 0

Answered

FPGA-in-the-Loop (FIL) Simulink Block Creation

Does your HDL code handle single datatype pixel input? You may want to try it with the appropriate fixed-point pixel data that t...

FPGA-in-the-Loop (FIL) Simulink Block Creation

Does your HDL code handle single datatype pixel input? You may want to try it with the appropriate fixed-point pixel data that t...

9 months ago | 0

Answered

How to plot n bit series of numbers. (n = 16 for example)

You can have a similar display using the dsp.LogicAnalyzer object. Here is the sample code I used: data = fi(rand(100,1),1,16,1...

How to plot n bit series of numbers. (n = 16 for example)

You can have a similar display using the dsp.LogicAnalyzer object. Here is the sample code I used: data = fi(rand(100,1),1,16,1...

10 months ago | 0

Answered

Is there any hdl library available for pulse generator. If yes please tell me the link

You can use the NCO HDL Optimized block to generate sine or cosine waves. Other repetitve waveforms can be genrated using a RAM...

Is there any hdl library available for pulse generator. If yes please tell me the link

You can use the NCO HDL Optimized block to generate sine or cosine waves. Other repetitve waveforms can be genrated using a RAM...

11 months ago | 0

Answered

conv2 'valid' implementation

You can use the MATLAB workflow in the example for image filtering.

conv2 'valid' implementation

You can use the MATLAB workflow in the example for image filtering.

11 months ago | 0

Answered

conv2 'valid' implementation

If you are looking for conv2 for image filtering, you can use the ImageFilter <https://www.mathworks.com/help/visionhdl/ref/imag...

conv2 'valid' implementation

If you are looking for conv2 for image filtering, you can use the ImageFilter <https://www.mathworks.com/help/visionhdl/ref/imag...

12 months ago | 0

Answered

Size mismatch using reshape in HDL Coder

Could you try assigning the value to a different variable rather than back to A. Ar = reshape(A,8,8); use Ar in the code bel...

Size mismatch using reshape in HDL Coder

Could you try assigning the value to a different variable rather than back to A. Ar = reshape(A,8,8); use Ar in the code bel...

12 months ago | 0

| accepted

Answered

For HDL code generation, the float point to fixed point conversion is ok. Because of "Accounting for output port latency: 10 cycles", the test bench does not agree with the HDL code. How to solve this problem?

It appears that delay balancing cannot balance the delays added because the added delays are in a feedback loop. If you can shar...

For HDL code generation, the float point to fixed point conversion is ok. Because of "Accounting for output port latency: 10 cycles", the test bench does not agree with the HDL code. How to solve this problem?

It appears that delay balancing cannot balance the delays added because the added delays are in a feedback loop. If you can shar...

12 months ago | 0

Answered

For HDL code generation, the float point to fixed point conversion is ok. Because of "Accounting for output port latency: 10 cycles", the test bench does not agree with the HDL code. How to solve this problem?

The HDL testbench will account for this latency. So generating the HDL code and testbench will let you run the modified testbenc...

For HDL code generation, the float point to fixed point conversion is ok. Because of "Accounting for output port latency: 10 cycles", the test bench does not agree with the HDL code. How to solve this problem?

The HDL testbench will account for this latency. So generating the HDL code and testbench will let you run the modified testbenc...

12 months ago | 0

| accepted

Answered

Matlab Simulink hardware design - Do we need a third party simulator?

You can run the generated HDL and testbench in the vivido simulator. However, if you want to run HDL cosimulation (that is, runn...

Matlab Simulink hardware design - Do we need a third party simulator?

You can run the generated HDL and testbench in the vivido simulator. However, if you want to run HDL cosimulation (that is, runn...

12 months ago | 0

Answered

I want to convert matlab code to verilog for my image processing project using hdl coder, i have the code but i dont know how to divide my code into function and test bench, please help me. I m using matlab r2018a version.

<https://www.mathworks.com/examples/vision-hdl/mw/visionhdl-ex64676005-accelerate-a-pixel-streaming-design-using-matlab-coder He...

I want to convert matlab code to verilog for my image processing project using hdl coder, i have the code but i dont know how to divide my code into function and test bench, please help me. I m using matlab r2018a version.

<https://www.mathworks.com/examples/vision-hdl/mw/visionhdl-ex64676005-accelerate-a-pixel-streaming-design-using-matlab-coder He...

12 months ago | 1

| accepted

Answered

Is it possible for Filter Design HDL coder to generate a FIR filter whose sampling rate is higher than clock rate?

This is available with HDL Coder and the FIR block in DSP System Toolbox. Please take a look at this <https://www.mathworks.com...

Is it possible for Filter Design HDL coder to generate a FIR filter whose sampling rate is higher than clock rate?

This is available with HDL Coder and the FIR block in DSP System Toolbox. Please take a look at this <https://www.mathworks.com...

12 months ago | 0

| accepted

Answered

HDL Sinusiod with phase offset and variable frequency

You may be able to use the <https://www.mathworks.com/help/dsp/ref/ncohdloptimized.html HDL Optimized NCO> to meet your needs.

HDL Sinusiod with phase offset and variable frequency

You may be able to use the <https://www.mathworks.com/help/dsp/ref/ncohdloptimized.html HDL Optimized NCO> to meet your needs.

1 year ago | 0

Answered

Simulink: How to implement an SRRC filter in HDL coder?

You can use <https://www.mathworks.com/products/filterhdl/features.html Filter Design HDL Coder> to implement a Farrow or an FIR...

Simulink: How to implement an SRRC filter in HDL coder?

You can use <https://www.mathworks.com/products/filterhdl/features.html Filter Design HDL Coder> to implement a Farrow or an FIR...

1 year ago | 0

Answered

Dual Port Ram - Output Port Widths or Dimension Error

Please try putting a signal specification block before each of the RAM inputs. Make sure that each signal specification block ha...

Dual Port Ram - Output Port Widths or Dimension Error

Please try putting a signal specification block before each of the RAM inputs. Make sure that each signal specification block ha...

1 year ago | 0

Answered

How to avoid the division operator from hdlcoder?

You can try using the <https://www.mathworks.com/help/simulink/slref/hdlreciprocal.html HDL reciprocal block> followed by a mult...

How to avoid the division operator from hdlcoder?

You can try using the <https://www.mathworks.com/help/simulink/slref/hdlreciprocal.html HDL reciprocal block> followed by a mult...

1 year ago | 0

Answered

HDL NCO: How do I set the fraction length for the phase accumulator?

The accumulator and quantizer do not have fractional bits. You can scale your input phase offset to match the accumulator and qu...

HDL NCO: How do I set the fraction length for the phase accumulator?

The accumulator and quantizer do not have fractional bits. You can scale your input phase offset to match the accumulator and qu...

1 year ago | 0

| accepted

Answered

HDL Coder Filter - Latency and Clock rate

I assume that you are sharing resources in the filter implementation leading to the 201x clock requirement. If your design sy...

HDL Coder Filter - Latency and Clock rate

I assume that you are sharing resources in the filter implementation leading to the 201x clock requirement. If your design sy...

1 year ago | 0

Answered

Why my Integer Fir on filterbuilder gives me zero coefficients?

Could you post the coefficients (at least the min/max values)? What is your input data type? For implementation onto an FPGA, y...

Why my Integer Fir on filterbuilder gives me zero coefficients?

Could you post the coefficients (at least the min/max values)? What is your input data type? For implementation onto an FPGA, y...

1 year ago | 0

Answered

HDL Coder Filter - Latency and Clock rate

The latency of 3 samples is not the group delay of the filter. It specified the number of pipeline delays in the data processing...

HDL Coder Filter - Latency and Clock rate

The latency of 3 samples is not the group delay of the filter. It specified the number of pipeline delays in the data processing...

1 year ago | 0

Answered

HDL workflow Advisor image

This <https://www.mathworks.com/products/vision-hdl.html Vision HDL Toolbox page> shows the capabilities provided for image proc...

HDL workflow Advisor image

This <https://www.mathworks.com/products/vision-hdl.html Vision HDL Toolbox page> shows the capabilities provided for image proc...

1 year ago | 0

Answered

Lane Detection with Zynq-Based Hardware - Pixel-Stream Model

You also need to download the <https://www.mathworks.com/hardware-support/zynq-vision.html Xilinx Zynq Support from Computer Vis...

Lane Detection with Zynq-Based Hardware - Pixel-Stream Model

You also need to download the <https://www.mathworks.com/hardware-support/zynq-vision.html Xilinx Zynq Support from Computer Vis...

1 year ago | 0

| accepted

Answered

Generating Verilog for Butterworth IIR lowpass filter, incorrect simulation

Can you try running the HDL code and testbench in ModelSim to see if it passes? If it does, that means that HDL code matches the...

Generating Verilog for Butterworth IIR lowpass filter, incorrect simulation

Can you try running the HDL code and testbench in ModelSim to see if it passes? If it does, that means that HDL code matches the...

1 year ago | 0

Answered

buffer block inside enabled subsystem

What is the purpose of using the buffer block in an enabled subsystem? You cannot really have 512 samples coming out of an FPGA ...

buffer block inside enabled subsystem

What is the purpose of using the buffer block in an enabled subsystem? You cannot really have 512 samples coming out of an FPGA ...

1 year ago | 0

Answered

this is our matlab code for image enhancement using power law at gamma=1.01,but we are getting error in function while compiling due to floating number(1.01).we are able to convert to verilog code using hdl coder at gamma=1 but not at gamma=1.01.help

You can use the Lookup table implementation for the <https://www.mathworks.com/help/visionhdl/ref/gammacorrector.html Gamma Corr...

this is our matlab code for image enhancement using power law at gamma=1.01,but we are getting error in function while compiling due to floating number(1.01).we are able to convert to verilog code using hdl coder at gamma=1 but not at gamma=1.01.help

You can use the Lookup table implementation for the <https://www.mathworks.com/help/visionhdl/ref/gammacorrector.html Gamma Corr...

1 year ago | 0

Answered

buffer quivalent block in HDL coder

Starting in R2018a, you can choose natural or bit-reversed order for the FFT block with vector input.

buffer quivalent block in HDL coder

Starting in R2018a, you can choose natural or bit-reversed order for the FFT block with vector input.

1 year ago | 0

Answered

buffer quivalent block in HDL coder

If you are using the <https://www.mathworks.com/help/dsp/ref/ffthdloptimized.html HDL Optimized FFT block> , I suggest you use a...

buffer quivalent block in HDL coder

If you are using the <https://www.mathworks.com/help/dsp/ref/ffthdloptimized.html HDL Optimized FFT block> , I suggest you use a...

1 year ago | 0