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HDL code to simulink model
You can use an HDL Cosimulation block to import this into Simulink. Here is a video and documentation for the procedure.

1 year ago | 0

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How to generate HDL serial filter architecture form Digital Down-Converter example
It does not apply to the CIC, please try it for the FIR Filter.

1 year ago | 0

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How can I figure out how many delay units do I need in one part of Simulink HDL design?
One of the ways to do this is by logging the input and output signals to the Logic Analyzer. You can set your cursors on the inp...

1 year ago | 0

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How to generate HDL serial filter architecture form Digital Down-Converter example
You can take each of the filters through the process of HDL code generation to control how many resources to use. To do so, run ...

1 year ago | 0

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Problem Using/Doing FFT HDL Optimized
Please take a look at this example which shows how to use the HDL Optimized FFT block.

1 year ago | 0

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HDL Coder disable Clock Enable output port
There is not a separate option - it is assumed that a requirement of a clock enable on the input would mean one is desired on th...

1 year ago | 0

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HDL Coder disable Clock Enable output port
You can use the option Minimize Clock Enables to remove the clock enable port. The clock enable typically cannot be removed for ...

1 year ago | 0

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Is it possible to get a conceptual explanation of how the scanning window filter work using the HDL pixel stream interface
The Line Buffer block help page has a brief description of its algorithm. The page also also has an example on how to construct ...

1 year ago | 0

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HDL COSIMULATION is taking too long time
You can use he FIL Frame To Pixels and FIL Pixels To Frame blocks - these send in multiple pixels at at time a line or frame at ...

1 year ago | 0

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FFT on FPGA using HDL coder
You can use the HDL Optimized FFT block for HDL code generation. Can you clarify on what challenges you face for fixed point co...

1 year ago | 0

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How can I create a subsystem which performs the opposite of the Multiport Switch block?
What output do you expect for each of these output signals in HDL? Say you have 10 outputs, your input is 1, and you want to se...

1 year ago | 0

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Estimating the latency of a custom IP block in HDL Coder
One of the ways to do this is by having the computatiobn block emit a valid output signal. based on this signal, the controller ...

1 year ago | 0

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HDL Coder VHDL Output
fix14 implies that there are 14 bits in total. u implies unsigned. En15 indicates that the LSB has a value of 2^-15, with an in...

1 year ago | 0

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How to profile an HDL Subsystem?
If you synthesize your HDL design in the appropriate HDL tool (example: Vivado), you will know what clock speed you can run the ...

1 year ago | 0

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how to generate sine wave for fpga?
You can use the self-guided tutorial on HDL Coder to see how to use the tool. The HDL Optimized NCO block in Simulink will allow...

1 year ago | 0

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FPGA-in-the-Loop (FIL) Simulink Block Creation
Does your HDL code handle single datatype pixel input? You may want to try it with the appropriate fixed-point pixel data that t...

1 year ago | 0

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How to plot n bit series of numbers. (n = 16 for example)
You can have a similar display using the dsp.LogicAnalyzer object. Here is the sample code I used: data = fi(rand(100,1),1,16,1...

1 year ago | 0

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Is there any hdl library available for pulse generator. If yes please tell me the link
You can use the NCO HDL Optimized block to generate sine or cosine waves. Other repetitve waveforms can be genrated using a RAM...

1 year ago | 0

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conv2 'valid' implementation
You can use the MATLAB workflow in the example for image filtering.

1 year ago | 0

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conv2 'valid' implementation
If you are looking for conv2 for image filtering, you can use the ImageFilter <https://www.mathworks.com/help/visionhdl/ref/imag...

1 year ago | 0

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Size mismatch using reshape in HDL Coder
Could you try assigning the value to a different variable rather than back to A. Ar = reshape(A,8,8); use Ar in the code bel...

1 year ago | 0

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For HDL code generation, the float point to fixed point conversion is ok. Because of "Accounting for output port latency: 10 cycles", the test bench does not agree with the HDL code. How to solve this problem?
It appears that delay balancing cannot balance the delays added because the added delays are in a feedback loop. If you can shar...

1 year ago | 0

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For HDL code generation, the float point to fixed point conversion is ok. Because of "Accounting for output port latency: 10 cycles", the test bench does not agree with the HDL code. How to solve this problem?
The HDL testbench will account for this latency. So generating the HDL code and testbench will let you run the modified testbenc...

1 year ago | 0

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Answered
Matlab Simulink hardware design - Do we need a third party simulator?
You can run the generated HDL and testbench in the vivido simulator. However, if you want to run HDL cosimulation (that is, runn...

1 year ago | 0

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I want to convert matlab code to verilog for my image processing project using hdl coder, i have the code but i dont know how to divide my code into function and test bench, please help me. I m using matlab r2018a version.
<https://www.mathworks.com/examples/vision-hdl/mw/visionhdl-ex64676005-accelerate-a-pixel-streaming-design-using-matlab-coder He...

1 year ago | 1

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Is it possible for Filter Design HDL coder to generate a FIR filter whose sampling rate is higher than clock rate?
This is available with HDL Coder and the FIR block in DSP System Toolbox. Please take a look at this <https://www.mathworks.com...

1 year ago | 1

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HDL Sinusiod with phase offset and variable frequency
You may be able to use the <https://www.mathworks.com/help/dsp/ref/ncohdloptimized.html HDL Optimized NCO> to meet your needs.

1 year ago | 0

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Simulink: How to implement an SRRC filter in HDL coder?
You can use <https://www.mathworks.com/products/filterhdl/features.html Filter Design HDL Coder> to implement a Farrow or an FIR...

2 years ago | 0

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Dual Port Ram - Output Port Widths or Dimension Error
Please try putting a signal specification block before each of the RAM inputs. Make sure that each signal specification block ha...

2 years ago | 0

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How to avoid the division operator from hdlcoder?
You can try using the <https://www.mathworks.com/help/simulink/slref/hdlreciprocal.html HDL reciprocal block> followed by a mult...

2 years ago | 0

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