Test bench can't work for some 'entity' are not compiled in library 'xil_defaultlib'.

I got the VHDL code using the System Generator, but there are some errors displayed as following figures. And the verilog HDL code could work generating from the same Simulink Model. Is there any setting should be done?Thank you very much.

Answer 1

[Bharath Venkataraman]

System Generator is a third-party blockset provided by Xilinx. For any further questions, please contact Xilinx technical support:

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