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Simulink: How to implement an SRRC filter in HDL coder?
You can use <https://www.mathworks.com/products/filterhdl/features.html Filter Design HDL Coder> to implement a Farrow or an FIR...

2 years ago | 0

Answered
Dual Port Ram - Output Port Widths or Dimension Error
Please try putting a signal specification block before each of the RAM inputs. Make sure that each signal specification block ha...

2 years ago | 0

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How to avoid the division operator from hdlcoder?
You can try using the <https://www.mathworks.com/help/simulink/slref/hdlreciprocal.html HDL reciprocal block> followed by a mult...

2 years ago | 0

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HDL NCO: How do I set the fraction length for the phase accumulator?
The accumulator and quantizer do not have fractional bits. You can scale your input phase offset to match the accumulator and qu...

2 years ago | 0

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Answered
HDL Coder Filter - Latency and Clock rate
I assume that you are sharing resources in the filter implementation leading to the 201x clock requirement. If your design sy...

2 years ago | 0

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Why my Integer Fir on filterbuilder gives me zero coefficients?
Could you post the coefficients (at least the min/max values)? What is your input data type? For implementation onto an FPGA, y...

2 years ago | 0

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HDL Coder Filter - Latency and Clock rate
The latency of 3 samples is not the group delay of the filter. It specified the number of pipeline delays in the data processing...

2 years ago | 0

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HDL workflow Advisor image
This <https://www.mathworks.com/products/vision-hdl.html Vision HDL Toolbox page> shows the capabilities provided for image proc...

2 years ago | 0

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Lane Detection with Zynq-Based Hardware - Pixel-Stream Model
You also need to download the <https://www.mathworks.com/hardware-support/zynq-vision.html Xilinx Zynq Support from Computer Vis...

2 years ago | 0

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Answered
Generating Verilog for Butterworth IIR lowpass filter, incorrect simulation
Can you try running the HDL code and testbench in ModelSim to see if it passes? If it does, that means that HDL code matches the...

2 years ago | 0

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buffer block inside enabled subsystem
What is the purpose of using the buffer block in an enabled subsystem? You cannot really have 512 samples coming out of an FPGA ...

2 years ago | 0

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buffer quivalent block in HDL coder
Starting in R2018a, you can choose natural or bit-reversed order for the FFT block with vector input.

2 years ago | 0

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buffer quivalent block in HDL coder
If you are using the <https://www.mathworks.com/help/dsp/ref/ffthdloptimized.html HDL Optimized FFT block> , I suggest you use a...

2 years ago | 0

Answered
Delaying FFT by a specified delay factor in simulink
I suggest using the dual port RAM. You can write the output of the FFT into the RAM as available. The read port will be controll...

2 years ago | 0

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Issue : Can't find SimpleDualPortRAM_generic-verilog.pvl
Could you print out a list of source files generated by HDL Coder and upload the model? It seems that the Dual Port RAM code was...

2 years ago | 0

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how to give vector as input to complex to magnitude angle hdl block
You can pass in the 64x1 samples to the <https://www.mathworks.com/help/dsp/ref/unbuffer.html Unbuffer block> which will send ou...

2 years ago | 0

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HDLCODER support function invoke function?
You can run this through the HDL code generation workflow. Any functions that are supported for HDL will generate HDL code. Func...

2 years ago | 0

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Answered
How to use extended word length and fraction in HDLFFT?
Satish, I am not able to reproduce the error. Here is my code. close all N = 8; ddc_out = randi([0 1],8,1); y_f...

2 years ago | 1

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No system or file called 'FFTHDLOptimizedExample_Burst' found.
You will need the DSP System Toolbox product for this example. Type *_ver dsp_* at the MATLAB prompt to see if you have this pro...

2 years ago | 0

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How to use fft in matlab hdl code to generate hdl code
Here is an <https://www.mathworks.com/help/dsp/examples/generate-hdl-code-for-fft-hdl-optimized-block.html example> of how to ge...

2 years ago | 0

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Triggering video stream with AND gate.
I believe that Kiran is asking you to put the enabled subsystem into a subsystem. TO do this, select the enabled subsystem and h...

3 years ago | 0

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How to generate Sine and triangle wave using HDL blockset?
You can use the <https://www.mathworks.com/help/dsp/ref/ncohdloptimized.html NCO HDL Optimized block> to generate a Sine wave. ...

3 years ago | 0

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Answered
When would HDL Coder support FFT with run time configurable transform point size ?
Could you please give some use cases for support so that we can consider the request for future releases?

3 years ago | 0

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Why my output image file turn out grayscale?
You have two issues with your model. # Change the Output Buffer Size setting for the Buffer block to 512*512*3. # Instead of...

3 years ago | 0

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How to set input and output data types separately for a filter when using generatehdl()?
The output of cicCompCascade is the output of the filter, and this is what Filter Design HDL Coder uses as the output type. Plea...

3 years ago | 0

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questions about Filter Design HDL Coder
Hi, You can post your question here or contact MathWorks support. Thanks, Bharath

3 years ago | 0

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All filter coefficients not used in HDL code
coeff2 has been recognized as a power of 2, and so implemented using a shift. No multiply is needed for this operation.

3 years ago | 0

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Answered
error input uint8 simulink
You can try using the <https://www.mathworks.com/help/dsp/ref/signalfromworkspace.html Signal From Workspace> block instead. I t...

3 years ago | 0

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How do I modify dsp.HDLFFT generated RTL to create smaller FFTs?
Are you trying to reuse the code for variable length FFTs? If all you want is FFTs of different sizes, you can configure dsp.HD...

3 years ago | 0

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