Difference in the output of CIC decimator while using with unbuffer and without unbuffer

I am using a CIC decimator block to downsample a high sample rate signal . the CIC decimator output is quite diffrent when i use it without unbuffer. but as for the FPGA apllication i need to unbuffer data the output is changed what could be the possible reason for this ? and how it could be resolved

Answer 1

[Bharath Venkataraman]

Could you please provide a model that shows this behavior (you may want to try it using a fixed known input first)?

Are you sending in the input as a Mx1 array (sending it in as a 1xN array will have the block interpret it as multi-channel data).

[muhammad ahmad]

i have tried different methods just to check if the signal being available on the input of CIC decimator is not shifted but it has an odd behaviour like the data after the input in fpga is showing some sort of sift in signals but that is not regular . can you please guide me in little detail how can i check the data propagting in FPGA as we can check in normal simulink simulation using specturum analyzer

[Bharath Venkataraman]

I want to make sure I have the problem understood correctly.

1. You have a Simulink model with the CIC Decimator that simulates correctly.
2. You generated HDL code and put it on the FPGA.
3. On the FPGA, you are finding discrepancies.

If the above is true, please try using the FPGA in the Loop workflow. This will run the HDL code on the FPGA but get data in and out of Simulink. It is a good way to verify that the HDL code runs on the FPGA correctly.

On the FPGA, you can also use FPGA data capture to capture data going in and out of the filter.

[muhammad ahmad]

yup you have understood problem correctly. let me try the options you have asked for