Hierarchical Designs and Synchronous Hardware Behavior
The HDL Coder block library contains many blocks that you can add to your Simulink® modeling environment and develop your HDL algorithm. To model large designs, you can divide your model into subsystems and create hierarchical designs. For synchronous hardware behavior and to generate hardware-friendly HDL code, use the State Control block inside the subsystems.
To filter the Simulink Library Browser to show only HDL-supported blocks, enter
hdllib. The blocks listed in this section
include those blocks that are only available in the
HDL Coder library. Blocks such as Foreach Subsystem
and Atomic Subsystem are available in the Simulink
library in the Library Browser.
For a filtered list of Simulink blocks supported for HDL code generation, see Simulink Block List (HDL Code Generation).
|Display blocks that are compatible with HDL code generation|
Simulink Configuration Parameters
|Unit Delay Enabled Synchronous||Delay input signal by one sample period when external Enable signal is true|
|Unit Delay Resettable Synchronous||Delay input signal by one sample period when external Reset signal is false|
|Unit Delay Enabled Resettable Synchronous||Delay input signal by one sample period when external Enable signal is true and external Reset signal is false|
|State Control||Specify synchronous reset and enable behavior for blocks with state|
|Synchronous Subsystem||Represent subsystem that has synchronous reset and enable behavior|
|Enabled Synchronous Subsystem||Represent enabled subsystem that has synchronous reset and enable behavior|
|Resettable Synchronous Subsystem||Represent resettable subsystem that has synchronous reset and enable behavior|
What is a State Control Block and how does it generate cleaner HDL code
Generate HDL code for subsystems that use array of buses in the design.
Generate shared code for identical subsystems or subsystems identical except for their mask parameter values
generic or Verilog®
parameter for model arguments in a model reference.
An example that shows how to model and generate HDL code for blocks inside a For Each Subsystem.
Model referencing in your DUT subsystem enables you to: