How to Generate Multicycle Path Constraints in HDL Coder
In designs with multiple sample rates that become multiple clocks in HDL, clock domain crossing can lead to timing violations in RTL synthesis. Discover how multicycle path constraints generated automatically from HDL Coder™ can help eliminate these violations, without design changes.
You will learn:
- What a clock period in digital hardware is
- What a critical path is and how it is measured
- Strategies to address critical path timing violations
- Cases where you can use multicycle path constraints
- How to automatically generate multicycle path constraints in HDL Coder
Published: 28 Mar 2018
Featured Product
HDL Coder
Select a Web Site
Choose a web site to get translated content where available and see local events and offers. Based on your location, we recommend that you select: .
You can also select a web site from the following list
How to Get Best Site Performance
Select the China site (in Chinese or English) for best site performance. Other MathWorks country sites are not optimized for visits from your location.
Americas
- América Latina (Español)
- Canada (English)
- United States (English)
Europe
- Belgium (English)
- Denmark (English)
- Deutschland (Deutsch)
- España (Español)
- Finland (English)
- France (Français)
- Ireland (English)
- Italia (Italiano)
- Luxembourg (English)
- Netherlands (English)
- Norway (English)
- Österreich (Deutsch)
- Portugal (English)
- Sweden (English)
- Switzerland
- United Kingdom (English)
Asia Pacific
- Australia (English)
- India (English)
- New Zealand (English)
- 中国
- 日本Japanese (日本語)
- 한국Korean (한국어)