Jack Erickson, MathWorks
The 5G NR HDL Cell Search reference application is hardware-proven subsystem IP that performs OFDM demodulation and detects primary and secondary synchronization signals (PSS/SSS). The hardware subsystem is designed using Simulink, and can be used as-is or modified to detect the signal synchronization block (SSB) information for use in your 5G wireless application.
This video outlines the design methodology used to create it, as well as how to simulate it and generate synthesizable RTL for FPGA or ASIC implementation. Details include:
This is a brief overview of the NR HDL Cell Search reference application, which is our first hardware-proven 5G subsystem IP in Wireless HDL Toolbox.
This is a hardware-optimized implementation of the PSS search, OFDM demodulation, and SSS search algorithms from this 5G Toolbox example. Because this needs to work for real-world over-the-air signals, it includes a digital down converter for mixing to baseband and changing sample rate.
The reference application was developed using a typical workflow for implementing wireless algorithms in hardware. It starts off with MATLAB code, and since this is a 5G algorithm it uses functionality from 5G Toolbox.
The input waveform is generated from this MATLAB function, also included in this reference application. Then noise and offset are added.
On the output side, the MATLAB code will initially display and plot the results. In this diagram, the blue boxes represent test bench elements and the orange represents design. It’s important to do this partitioning early to make it easier to swap in and compare versions with more implementation detail, which is what the hardware architecture MATLAB code is here.
This is partitioned at a high level between what will be implemented as hardware and as software. The hardware portion is run in two phases. The first – search mode – takes in the waveform along with a coarse estimate for frequency offset and the desired subcarrier spacing, and performs PSS detection, returning the correlation results for the three possible PSS values. Search mode allows the software to coordinate a search for PSS (or cells) at different coarse frequency offsets and subcarrier spacings. The software determines the strongest PSS correlation, corresponding to the strongest cell, then calls the hardware again in demodulation mode, passing this PSS info for the hardware to perform OFDM demodulation and SSS detection, returning those results.
There’s also a MATLAB structure of diagnostic signals that gets routed to the top level. This structures the design nicely to later bring these signals up to the top level of the FPGA.
We still need to adapt these algorithms to work on a continuous stream of signal data, as they would in hardware. Simulink is the best environment for that because it models timing. In this design, the MATLAB testbench drives the Simulink model’s inputs. They get converted to a stream of samples, then back to frames on the output for comparison versus that MATLAB hardware reference algorithm, which in this stage is the reference the testbench will use to verify.
The MATLAB data is passed via the From Workspace blocks here, and the outputs collected for MATLAB in these To Workspace blocks. While we drive the test bench using MATLAB, being able to visualize the architecture and data type propagation makes Simulink more conducive to adding the streaming hardware behavior to the design. Just as with the MATLAB reference, the incoming waveform moves through the DDC to PSS detection in the first mode. The results are returned to the MATLAB testbench acting as the software, and then driven back into the hardware in demodulation mode, where it’s sent into the OFDM demodulator, a hardware-ready block you can just plug in and configure. The demodulated grid is output, and also sent into SSS detection, with the results all registered at the system output and returned to MATLAB. You can also see the collecting of diagnostic info for output to the top level.
We can kick off the simulation from MATLAB. As it starts it generates a plot for the generated test waveform, that shows the combined resource grid of all eight SSBs in the transmitted waveform. The simulation takes a few minutes since it runs both MATLAB and Simulink, in each mode, so we can skip ahead and see the results. First the cell search mode results showing PSS0 as the strongest cell, then a nice clean peak from the SSS correlator, and finally the spectrogram showing the demodulated symbols that follow PSS, with SSS in the center 127 resource elements of the second symbol. All of these results and the diagnostics are returned to the MATLAB workspace for analysis.
At this point we can generate HDL code and run FPGA synthesis. Make sure we have the right subsystem set here. You can run FPGA synthesis directly from the HDL Workflow Advisor, starting with the target device and frequency, which we set to 150 MHz to give us some margin over the 112.88 MHz 5G-compatible rate. Then the HDL Workflow Advisor guides you through the full workflow and option setting. This takes a little while to run through synthesis….and looking at the results, it was able to easily meet the 150 MHz target post-synthesis with the resource usage shown here.
This hardware subsystem is set up as a model reference, so you can either use it as-is or make your own modifications, and have it return synchronization signal information to your 5G-based application.
The reference application overview provides more detail, and the design itself is available in Wireless HDL Toolbox.