Reference applications form a basis for designing, simulating, and deploying computer vision applications on FPGA, ASIC, and SoC devices.
Perform Pixel-Streaming Design
Process 4k and 8k videos and manage input streaming data with built-in pixel control signals, ROI windows, and line buffers. Design and simulate efficient hardware architecture implementations using single or multipixel (2, 4, or 8 pixels per cycle) streaming of vision processing algorithms.
Prototype and Verify on FPGAs and SoCs
Build prototype design with live video input using AMD Zynq Hardware Support Package and model templates. Generate target independent synthesizable VHDL and Verilog code with HDL Coder for supported FPGA or SoC platform. Use HDL Verifier to test and debug your vision hardware designs.
“MATLAB and Simulink cut the time required in the development stage by half. The tools made it easy to respond to our OEM customer’s requirements by enabling the design of custom functions.”Jiyoung Jeong, LG Electronics