What are the best methods to speed up a simulation that uses a 5Mhz clock but needs to simulate 2 sec of run-time?
I am running a brushless DC motor in a phase lock loop (DPLL) simulation and am concerened with estimating jitter. My actual system uses a 50MHz clock in a FPGA. I am simulating with a 5MHz clock because I want a resolution of at least 0.2us on jitter estimates.
I am using a combination of S-functions and sub-sytems. I am using a boolean pulse generator at 5Mhz as the clock. My motor model is continuous time. I only run S-functions if the clock transitions low to high. I only run the phase detector on the rising edge of the reference or feedback as sampled with the rising edge of the boolean clock. The compensation, a digital filter, is an S-block that is only run if the phase detector state changes. The effective sample rate is 360Hz.
Because it is a mechanical system I need to simulate about 2 seconds of time to gather lock and seettle.