How to profile an HDL Subsystem?

I have a SIMULINK Model with a Subsytem which is running in PL. I would like to know its speed in terms of clock frequency or FramePerSecond (it is an image processing algorithm).

Any feedback or suggestion are accepted.

Thank you.

Best

Answer 1

[Bharath Venkataraman]

If you synthesize your HDL design in the appropriate HDL tool (example: Vivado), you will know what clock speed you can run the design at. Assuming you are processing one pixel per clock in the HDL, you should be able to calculate the frames per second.

[Andrea Foradori]

Thank you for your answer.

So could you please help me to understand what is (if it exists) the relationship between the "SIMULINK Model Sample Time" and the "HDL clock frequency".

I have good knowlege about VHDL/FPGA but I have few knowledge about SIMULINK.

Thank you in advance.

Best regards

[Bharath Venkataraman]

There does not need to be any relationship between the Simulink sample time and HDL clock frequency. You can choose the sample time to whatever you Some people choose to have this correlation, in which case you can set the sample time in one of the sources so that your HDL subsystem runs at the pixel clock rate.

By default, HDL Coder will use one clock based on the base sample time in the HDL subsystem. You can then choose to put your constraint on that clock in the synthesis tool.

For the attached model, you can set the Desired sample time for the Video Source block to totalPixels=130248, which is 402*324, the total number of pixels: see Video Format section in this page). This sets the sample time of the pixel input to the HDL Algorithm subsystem to 1.

You can also set Desired sample time for the Video Source block to 1, which will change the sample time of the pixel input to HDL Algorithm subsystem to 7.6777e-6 (1/(402*324)).

In both cases, the HDL code generated will be the same. For 240p @ 60fps, you can hook up a clock of 7.814880 MHz, which is 402*324*60.