How can I force HDL Coder to use DSP48 slices?

Even though for simple examples, the inclusion of synthesis attributes such as syn_multstyle(synplify) or use_dsp48(vivado) is enough to ensure that the DSP slices are effectively used, these synthesis attributes seem to not work with more complex projects. Thus, how do you recommend to make sure that the DSP slices are being used. I activated pipeline in every expression (through hdl.coder.pipeline(...)) and I activated the Input/Output registers. In the end, I want to have a project independent from the device, so I do not want to manually instantiate the DSP. I know that in System Generator you have some flags in the modules to force the use of embedded multipliers, do not we have the same in HDL Coder? In the end, my synthesis tools are just using a small percentage of DSP (0.3%) putting the remaining logic in CARRY8 and LUTs giving to me a high critical path, which I can not afford to this specific application. Looking forward to hearing from you,

Answer 1

[Kiran Kintali]

if you are looking to automate DSP usage improvements you can consider using Adaptive pipelining optimization in HDL Coder.

Adaptive Pipelining

Certain patterns or combination of blocks with registers can improve the achievable clock frequency and reduce the area usage on the FPGA boards. The adaptive pipelining optimization creates these patterns by inserting pipeline registers to the blocks in your design. To determine the optimal number of pipeline registers to insert in your design, the optimization considers the target device, target frequency, multiplier word lengths, and the settings in the HDL Block Properties. This careful insertion of pipelines helps in DSP inference durin gsynthesis.

[Aunullah Qaiser]

Your answer isn't what is asked in the question. If you do not understand the question, ask for an elaboration. Please don't answer just for the sake of answering without even understanding the question.

[Kiran Kintali]

The response was based on two key objectives in the original post.

>> In the end, I want to have a project independent from the device, so I do not want to manually instantiate the DSP

>> In the end, my synthesis tools are just using a small percentage of DSP (0.3%) ...

Adaptive Pipelining is a good place to start to be target independent and achieve best DSP mapping in the final generated code. Please see the supported blocks where pipelines are added to increase chances of DSP Mapping https://www.mathworks.com/help/hdlcoder/ug/adaptive-pipelining-1.html

Based on the Target Device Settings, Adaptive pipelining implicitly understand the DSP architectures and modeling idioms of the synthesis tools when deciding the place to insert pipelinines and balancing them.

One can force DSP mapping by manually inserting pipelines in the model or code (using delay blocks) but this would mean you are simulating the algorithm with pipelinine latency which may or may not be desirable.

Adaptive Pipelining is a way keep the algorithm independent of hardware archtecture details.

Answer 2

[Aunullah Qaiser]

Posting this if someone else is looking for Efficient mapping to DSP blocks in FPGA.

https://in.mathworks.com/help/hdlcoder/ug/modeling-efficient-multiplication-and-division-operations-for-fpga-targeting.html