Delaying FFT by a specified delay factor in simulink

How do I delay FFT samples by a specified delay factor in Simulink?

FFT output length [32768x1] appearing one value at a time (as a scalar). Delay factor length [32768x1] appearing one value at a time (also as a scalar).

So, basically each samples of my FFT should be delayed by the respective samples of the delay factor. To be simple and more clear, 1st sample of my FFT output should be delayed by the first value of the delay factor and 2nd by 2nd, 3rd by 3rd and so on...

The delay block with delay length as "Input Port" (which is my delay factor as a scalar) is not producing the output as expected.

This is the block parameters.

Please tell me any other means.

PS: Working on the blocks which are HDL compatible (HDL coder). The target is to implement on an FPGA

Thanks in advance

Sumukh

Answer 1

[Bharath Venkataraman]

I suggest using the dual port RAM. You can write the output of the FFT into the RAM as available. The read port will be controlled using a counter that can be configured to the appropriate delay. One way to do this is to read when the counter is 0 and have the counter count from 32767 the first time, from 32766 the second and so on.

One issue I see with this delay is that you are reading out slower than you are writing in. Are you sure that your next frame for the FFT is not coming in till you are done reading the current output? Otherwise the RAM will overflow.

[Sumukh Bharadwaj]

Hi, thank you very much for your valuable solution.

I cannot exactly use this block as our FPGA doesn't support parallel R/W operation but only sequential. So, a similar block called Single Port RAM will do the job. And I'm working on it...

Thanks for letting me know the methodology :-)

[Bharath Venkataraman]

Sumukh, I want to confirm that you truly want this gap between the FFT output samples. The FFT will come out with output samples every cycle. This is a sequential output that you can hook up to the net block.

The RAM will allow you to delay the output but the FFT output (RAM input) will still run far faster than the RAM output.

I suggest that you enable the FFT start output port. You should only store valid values into the RAM.

You can also use the HDL FIFO block , which uses push to put values in and pop to send values out.