Hi,
I am using HDL coder to doing a DSP design. The generated code for resettable register is strange. The connection of the register is shown in the diagram below.
when I generate the HDL code only for the sub model alone, the generated HDL code for the register is somehow correct, where "en1" is the enable signal, "Constant_out" is the input data to the register and "Delay2_out1" is the reset signal. Although I want to generate a synchronous reset, the last line make it an asynchronous reset. this is ONE problem.
Constant_out1 <= '1';
R1_process : PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF reset = '1' OR Delay2_out1 = '1' THEN
R1_switch_delay <= '0';
ELSIF enb = '1' AND en1 = '1' THEN
R1_switch_delay <= Constant_out1;
END IF;
END IF;
END PROCESS R1_process;
R1_out1 <= '0' WHEN Delay2_out1 = '1' ELSE
R1_switch_delay;
When I generate the HDL of the whole design which contains this sub model, the generated HDL code for the register is strange. It is not a resettable register any more, only when my reset "Delay2_out1" is "1" the output of the register is "0". otherwise it behaves like a delay.
Constant_out1 <= '1';
R1_iv <= '0';
R1_toDel <= Constant_out1 WHEN Delay2_out1 = '0' ELSE
R1_iv;
R1_ectrl <= R1_delOut WHEN en1 = '0' ELSE
R1_toDel;
-- <S50>/R1
R1_lowered_process : PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF reset = '1' THEN
R1_delOut <= '0';
ELSIF enb = '1' THEN
R1_delOut <= R1_ectrl;
END IF;
END IF;
END PROCESS R1_lowered_process;
R1_out1 <= R1_delOut WHEN Delay2_out1 = '0' ELSE
R1_iv;
All the configurations are same during the code generation. Why the generated results are different? The second one is apparently wrong. This is the SECOND problem.
regards, Qi
