AXI4-Stream to Software clock frequency does not match FPGA clock frequency

Dear all,

I am using SoC Blockset add-on and checking out the example "Transmit and Receive Tone Using RFSoC Device" (https://www.mathworks.com/help/soc/ug/transmit-and-receive-tone-using-RFSoC-device-simulate.html). The FPGA Clock frequency (SampleTime) is set to 128MHz, but the AXI4-Stream to Software clock is set to 200MHz. How are then all the samples written to memory if the memory clock is slower than the sample production frequency?

How does in general AXI4-Stream to Software block work? The following qustions are not answered in the documentation (https://www.mathworks.com/help/soc/ref/axi4streamtosoftware.html):

1) Does one buffer contatin multiple bursts? If yes, how many?

2) With what rate is burst written to buffer?

3) With what rate are samples saved in burst (to be written to buffer later)?

4) Are samples written to FIFO with the same rate as in the previous question?

Thank you!

Answer 1

[Jerome Chevalier]

Hi @Sergei,

"The FPGA Clock frequency (SampleTime) is set to 128MHz, but the AXI4-Stream to Software clock is set to 200MHz", so the memory clock is faster than the sample production frequency, not slower.

AXI4-Stream to Software block simulates the DMA data transfer between an AXI Stream and a memory. AXI4-Stream to Software block (similar to a real DMA) is buffering multiple sample from the stream and then write those sample together in one burst in the memory.

1) A buffer can contain 1 to N burst (with N being an integer)

2) Burst are written in memory when enough sample has been received from the stream to complete a full burst (or Tlast has been raised). Assuming stream valid is always high, no tlast, no memory contention, no sample format change (bit packing) : burst rate = stream rate / burst size

3)Sample are always "Saved" for next burst by the AXI4-Stream to Software block, unless there is no more buffer available in memory and the burst buffering FIFO is full.

4)Yes, sample are written into the FIFO at the stream rate. if the the FIFO is full, ready signal will go low and any further sample will be discarted until space in the FIFO is available and ready signal go high.

[Sergei]

Thank you a lot, Jerome Chevalier, your answer is explaining and comprehensive!

Although I still have the question of with which rate are samples "saved" into a burst: The one that I specify as a AXI4-Stream to Software parameter "Clock frequency" (Main --> Advanced --> Clock frequency), or the one that I specify as a AXI4-Stream to Software parameter "Sample time" (Signal Attributes --> Stream data signal --> Sample time)? What do we need the other one for then and what does it do during simulation and deployment on a hardware? Thank you!