zcu102: split tasks between the 4 available CPUs

Hi,

I'm doing some testing on a ZCU102. I followed a few examples and I was able to run HDL to split some programming between FPGA and CPU and run my model on the target. Based on the examples I found, as far as I understand, basically everything that is not processed via HDL goes on the CPU. The ZCU102 as a quadcore. I would like to try to split some tasks between them. I found a few examples like but when I go into Allow tasks to execute concurrently on target and I click Configure Tasks I cannot find the ZCU102 in the possible target applications and if I select custom it just shows one CPU. Is there something I'm missing? Is there an example I can follow?

thanks

Michele

Answer 1

[Kiran Kintali]

https://www.mathworks.com/help/hdlcoder/ug/getting-started-with-hardware-software-codesign-workflow-for-zynq-ultrascale-mpsoc-devices.html

You need to split the model into two subsystems or two model reference based blocks for hardware and software.

[TuttoAlDoc]

Hi, thanks for the answer. My question is different. Having a block for software how can I assing the activities in the software blocks to different CPUs considering I have 4 available?

[Kiran Kintali]

https://www.mathworks.com/help/simulink/examples.html?category=multicore-processor-targets&s_tid=CRUX_topnav

IP core workflow in HDL Coder generates SW interface subsystem as the subsystem to talk to the FPGA side.

This SW interface subsystem can be placed into your SW model to use Embedded Coder to build multi-core application.

There are different ways for Embedded Coder to build multi-core:

• Multi rate and Multitasking Mode (https://www.mathworks.com/help/rtw/ug/modeling-for-multitasking-execution.html)
• Explicit modeling of concurrent execution (https://www.mathworks.com/help/simulink/multicore-processor-targets.html?s_tid=CRUX_lftnav)

[TuttoAlDoc]

Thank you very much for your answer, I will have a look