Add 'MARK_DEBUG = "TRUE"' to signals in generated HDL
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Kevin Williams
on 19 Jun 2023
Answered: Kiran Kintali
on 16 Jul 2023
I need to mark certain signals in a verilog code generation with the attribute MARK_DEBUG = "TRUE",
for example:
(* MARK_DEBUG = "TRUE" *) wire [15:0] snapshot_addr; // uint16
How do I do this?
Many thanks, Kevin
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Accepted Answer
Kiran Kintali
on 16 Jul 2023
Currently synthesis attribute specification is limited to certain blocks like product block.
This capability is planned for ports, signals, subsystems and more blocks in the near future releases.
Please reach out to tech support for additional requests in this area.
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