Multiple outputs from HDL block in simulink

I want to take multiple outputs from one HDL block(in Simulink) simultaneously but it only has one output option port(I & Q) values as shown in the attached image.

Actually on the application side my target is zynq-706 and want to stream multiple Radio signals from FPGA(HDL block) simultaneously.But the block doesnt let me due to single output option.

Anybody having ideas or solutions are most welcome!!!!

Answer 1

[JT Ferrara]

Hi Muhammad,

HDL Coder supports generating an IP core with multiple AXI4-Stream channels. There are two ways to generate such as IP core:

1. Use generic IP core generation to generate just an IP core with multiple streaming channels, as described here: https://www.mathworks.com/help/hdlcoder/ug/map-dut-ports-to-multiple-axi-interfaces.html
2. Use a reference design that is preconfigured with multiple streaming channels, as shown in this example: https://www.mathworks.com/help/hdlcoder/ug/running-audio-filter-with-multiple-axi4-stream-channels.html

Note that specific Simulink blocks or reference design may have their own constraints on the number of streaming channels. But in general, this is possible.

Best,

JT

[muhammad ahmad]

Thank you for your response but i want to add something to my question

More preciesly, I have a single Fmcomms3 card with my Zynq-706 that scans a band of frequency(FM and AM) and yields a list of Active channels on the ARM processor side. Then on the HDL block i want to demodulate all the channels in this list simultaneously and want to stream different channels out of the HDL block simultaneously . what would be the way to do this using simulink and zynq?

[JT Ferrara]

Hi Muhammad,

I suggest looking through these examples to help you get started on your design:

https://www.mathworks.com/help/supportpkg/xilinxzynqbasedradio/examples.html

Many of the examples should support running on ZC706 with FMCOMMS3.

Best,

JT

Answer 2

[Kiran Kintali]

Can you share your model? Thanks

[muhammad ahmad]

attached is the demodulator block for FM we need to pass out multiple channels(stations) out of the HDL block like this simoultaneously .how can we do this in simulink for zynq FPGA .

Thank You

Answer 3

[Kiran Kintali]

https://www.mathworks.com/help/hdlcoder/ug/getting-started-with-axi4-stream-interface-in-zynq-workflow.html

Getting Started with AXI4-Stream Interface in Zynq Workflow

This example shows how to use the AXI4-Stream interface to enable high speed data transfer between the processor and FPGA on Zynq hardware

Your usecase seems different, but this example seems relevant for the topic

FM Broadcast Receiver

This example shows how to build an FM mono or stereo receiver using Simulink® and Communications Toolbox™. You can either use captured signals, or receive signals in real time using the RTL-SDR or ADALM-PLUTO.

https://www.mathworks.com/help//supportpkg/rtlsdrradio/ug/fm-broadcast-receiver-1.html