PLL no lock

Hello everyone,

I made a simple PLL simulink model (link bellow). When the reference frequency is 2010Hz and the VCO is nominally at 2000Hz, the PLL locks successfully. However when the reference is 2020Hz (or more) the PLL does not lock but oscillates. I tried varying several of the model parameters but still no clue why this is so? Any idea or explanation would be appreciated.

http://www.sendspace.com/file/dddy8s

Greetings, PO

[Poky Poky]

No ideas? OK I went a little bit further and figured out that actually the loop filter should be a first order. Then everything with the lock range is as expected. Does anyone has an idea why the loop filter needs to be first order? I am new to this stuff, so simple explanation would be greatly appreciated.

Greeting,PO

Answer 1

[Pragati]

From the description, your PLL is locking for a small frequency offset but begins to oscillate when the reference frequency increases slightly. This is a common symptom of loop dynamics and stability limitations, rather than a modeling error.

In your specific case, the observation that switching to a first-order loop filter restores the expected lock behavior is a strong indication that loop filter design and loop bandwidth are the key factors governing lock range.

In general, a PLL will fail to lock or exhibit oscillations when:

• The loop bandwidth and phase margin are not sufficient for the given frequency offset
• The loop filter order or component values lead to instability
• The VCO tuning range or gain (KVCO) is not well matched to the loop dynamics

For example, incorrect loop filter design or bandwidth mismatch can prevent the loop from acquiring lock or cause oscillatory behavior.

So what you’re observing is consistent with a loop that is:

• Stable for small frequency errors
• But becomes underdamped or unstable when the required correction increases

This is precisely the type of issue that Mixed-Signal Blockset is designed to help debug at the system level before circuit implementation.

With Mixed-Signal Blockset, you can:

1. Model loop dynamics explicitly

You can build the PLL from individual components (PFD, charge pump, loop filter, VCO, dividers) or start from reference architectures and analyze the impact of loop filter order and parameters directly

2. Explore lock range and stability

Using system-level simulation, you can:

• Sweep reference frequency offsets
• Evaluate lock behavior (lock/no-lock, oscillation)
• Measure transient response and settling time

This makes it easier to reproduce exactly the behavior you’re seeing and understand where the loop loses stability.

3. Use measurements and testbenches

Mixed-Signal Blockset provides testbenches and measurement workflows to verify system-level performance (e.g., lock behavior, transient response) under different impairments

https://www.mathworks.com/help/msblks/phase-locked-loop.html?s_tid=CRUX_lftnav