Perform Analysis on Large and Complex Models

Some characteristics of Simulink^® models can cause problems during a Simulink Design Verifier™ analysis. This includes:

Complexity of model inputs due to large number of inputs, types of inputs, and the way the inputs affect the model state and the objectives of the analysis
Number of possible simulation paths through a model
Portions of the model that cannot be reached
Large counters in the model

Apart from this, the Simulink Design Verifier software may encounter some of these problems when analyzing a large model:

Unsatisfiable objectives — The software proved there are no test cases that exercise these test objectives, and did not generate any test cases.
Undecided objectives — The software was not able to satisfy or falsify these objectives.
Objectives with errors — This problem usually occurs when a model component uses non-linear arithmetic, which can affect a test objective.
Cannot complete the analysis in the time allotted — This problem may indicate an area of your model where the software encountered problems, or you may need to increase value of the Maximum analysis time parameter.
Analysis hangs — If the number of objectives processed remains constant for a considerable length of time, the software has likely encountered complexity between the model and its objectives.
Does not achieve a high percentage of model coverage — When you run the test cases on the harness model, the percentage of model coverage is insufficient for your design.

In larger, more complicated models, Simulink Design Verifier uses mathematical techniques to simplify the analysis by identifying portions of the model that do not affect the desired objectives, discovering relationships within the model that reduce the complexity of the search, and reusing intermediate results from one objective to another. In this way, the problem is reduced to a search through the logical values that describe your model. For detailed information about analyzing large models, see Perform Analysis on Large and Complex Models.

How Simulink Design Verifier Simplifies Analysis on Large Models

In larger and complicated models, Simulink Design Verifier uses mathematical techniques to simplify the analysis:

It identifies portions of the model that do not affect the desired objectives.
It discovers relationships within the model that reduce the complexity of the search.
It reuses intermediate results from one objective to another.

In this way, the problem is reduced to a search though the logical values that describe your model.

The next few sections describe the initial steps to take when analyzing a large model. Most of the techniques are used for reducing model complexity focus on test generation for large models. However, you can use many of them to detect design errors or prove the properties of a large model and generate counterexamples when a property is disproved.

Summarize Model Hierarchy and Compatibility Using Test Generation Advisor

You can use the Test Generation Advisor to summarize test generation compatibility, condition and decision objectives, and dead logic for the model and model components.

The Test Generation Advisor performs a high-level analysis and fast dead logic detection. You can use the results to better understand your model, particularly large models, complex models, or models for which you are uncertain of their compatibility with Simulink Design Verifier. For example, you can:

Identify incompatibilities with test case generation.
Identify complex components that might be time-consuming to analyze.
Determine instances of dead logic.
Get a summary of the component hierarchy.
Get recommended test generation parameters.

To access the Test Generation Advisor, on the Design Verifier tab, in the Mode section, click Test Generation. In the Prepare section, click Advisor. For more information see Use Test Generation Advisor to Identify Analyzable Components.

Use Default Parameter Values for Analysis

When you generate test cases, you should generally begin by analyzing the model using the Simulink Design Verifier default parameter values:

Check to see if your model is compatible with Simulink Design Verifier, as described in Check Model Compatibility for Analysis.

To analyze the model, use the default parameter values. The following table lists the default values for parameters in the Configuration Parameters dialog box that you might change when analyzing large models.

Parameter	Default Value	Description
Maximum analysis time (s)	`300` (seconds)	If the analysis does not finish within the specified time, the analysis times out and terminates.
Test suite optimization	`Auto`	Generates test cases that address more than one test objective.
Model coverage objectives	`Condition/Decision`	Generates test cases that achieve condition and decision coverage.

Review the following information in the Simulink Design Verifier log window while the analysis runs:
- Number of objectives processed — How many objectives were processed? Did the analysis hang after processing a certain number of objectives? The answers to these questions might give you a clue about where a problem might lie.
- Number of objectives satisfied/Number of objectives falsified — Which objectives were falsified?
- Time elapsed — Did the analysis time out, or did it finish within the specified maximum analysis time?
When the analysis completes, you can highlight the results in the model and individually review the analysis of each model object, as described in Highlight Results on the Model. You can also generate and review the Simulink Design Verifier HTML report. This report contains links to the model elements for satisfied and falsified objectives so you can see what portions of the model might have problems. For more information, see Review Results from Analysis Report.
For a test generation analysis, if all the test objectives have been satisfied, run the test cases on the harness model to determine model coverage.
If model coverage is enough for your design, you do not need to do anything else. If the coverage is insufficient, take additional steps to improve the analysis performance, as described in the following sections.

Note

A large percentage of falsified objectives and poor model coverage often indicate that you need to change model parameter values to get complete coverage. This can occur when you have tunable parameters in Constant blocks that are connected to enabled subsystems or to the trigger inputs of Switch blocks. In these situations, configure Simulink Design Verifier parameter support as described in the example Specify Parameter Configuration for Full Coverage.

Modify the Analysis Parameters

If the analysis satisfied most but not all of the objectives, try the following steps:

Increase the Maximum analysis time parameter. This gives the analysis more time to satisfy all the objectives.
Set the Model coverage objectives parameter to Decision. Selecting this option generates only test cases that achieve decision coverage. These test cases are a subset of the MCDC option.
Rerun the analysis and review the report.
If the results are still not satisfactory, try the techniques described in the following sections.

Stop the Analysis Before Completion

Watch the Objectives processed value in the log window. If about 50 percent of the Maximum analysis time parameter has elapsed and this value does not increase, the model analysis may have trouble processing certain objectives. If the analysis does not progress, take the following steps:

Click Stop in the log window.
A dialog box appears, informing you that the analysis was aborted and asking you if you still want to produce results.
Click Yes to save the results of the analysis so far.
The log window lists the following options, depending on which analysis mode you ran:
- Highlight analysis results on model
- Generate detailed analysis report
- Create harness model
- Simulate tests and produce a model coverage report
Click Generate detailed analysis report.
In the HTML report, review the following sections to identify the model elements that are causing problems:
- Objectives Undecided when the Analysis was Stopped
- Objectives Producing Errors

Review the model elements that have undecided objectives or objectives with errors to see if these problems are present. Consult the pages in the More Information column for specific techniques to improve the analysis.

Problem in Your Model	Workarounds
Floating-point inputs or non-linear operations	By default, Simulink Design Verifier may interpret data types as double, which can introduce precision issues during analysis. To improve analysis precision, specify data types explicitly when known and simplify data types where possible. Use integer data types for timers and counters, and avoid unnecessary cast operators to reduce non-linear operations. Constrain data type ranges by setting minimum and maximum values for model inputs or using the Test Condition or sldv.assume block to discretize input or signal ranges. For more information, see Manage Model Data to Simplify the Analysis, and Logical Operations Short-circuiting.
Large state spaces	Apply constraints to input signals that are delayed. Constrain the inputs to states that are contained within conditionally executed subsystems. Limit the number of test case steps by setting the Maximum test case step parameter to `20`. Increase the sample time for part or all of the model. (This procedure is similar to reducing timer thresholds, as described in Analyze Models with Counters and Timers.) A test case that you generate at a lower sample rate often has similarities to the test case with a high sample rate that you need to achieve an objective. Use tight variable types where ever possible. For example, if a flag with values of 0 or 1 only is defined as a `double`, restrict the type to `Boolean`. Alternatively, you can use existing simulation data to help satisfy your testing needs. If you have existing test data, run it on your model and collect model coverage. For an example of extending an existing test suite to achieve missing model coverage, see Extend an Existing Test Suite. Also see, Bottom-Up Approach to Model Analysis
Large timers and time delays	Use the workarounds mentioned in Analyze Models with Counters and Timers and Bottom-Up Approach to Model Analysis

Increase Allocated Memory for Analysis Report Generation

When you analyze a model with a large root-level input signal count, you may encounter an insufficient memory error when Simulink Design Verifier is generating the report.

When this occurs, you need to increase the amount of memory the Sun^® Java^® Virtual Machine (JVM^®) software can allocate. For steps on how to increase this memory, see Increase the MATLAB JVM Memory Allocation Limit (MATLAB Report Generator).