Simulink® Design Verifier™ considers logical operations and logical expressions as short-circuiting when analyzing for dead logic and when generating tests. For more information, see "Short-Circuiting of Boolean Expressions for MCDC" in Analyzing MCDC for Cascaded Logic Blocks (Simulink Coverage).
Consider the following example model, with the Model coverage
objectives parameter set to
Decision. In this case, when a previous input alone determines the block
output, the analysis ignores any remaining block
inputs. If the first input to a Logical Operator block whose
Operator parameter specifies
AND is false,
the analysis ignores the values of the other inputs.
When Simulink Design Verifier analyzes this model for Condition Decision coverage, the analysis can only satisfy five of six objectives for the Logical Operator block inputs. The software cannot generate a test case when the third input to the Logical Operator block is false. If the second input is false, the third input is false, but the software ignores the third input due to the short-circuiting. If the second input is true, the third input is never false.