Timing Analysis Reports

The Parallel Link Designer app lists results of the timing analysis in the Waveform and Timing Report. To launch the report, click Reports > Waveform and Timing Report at the end of the simulation. The report sorts the timing data in multiple tabs to organize them.

Timing Analysis Log Tab

The Timing Analysis Log tab of the timing analysis report for pre-layout and post-layout simulations contains a summary of timing results along with any errors or warnings that were generated while running the timing analysis.

Timing Tab

The Timing tab of the timing report for pre-layout and post-layout simulations rolls up the By Variation Details tab by combining all transitions in the same transfer net.

Column	Description
Setup Margin (ns)	Worst difference between receiver setup time for all simulations and the setup requirement in its timing model.
Hold Margin (ns)	Worst difference between receiver hold time for all simulations and the hold requirement in its timing model.
R_min Etch Delay (ns)	Minimum rising edge etch delay.
R_max Etch Delay (ns)	Maximum rising edge etch delay.
F_min Etch Delay (ns)	Minimum falling edge etch delay.
F_max Etch Delay (ns)	Maximum falling edge etch delay.
Transfer Net	The name of the transfer net.
Column	Contains the name of each variation group, with the column number for each variation group (pre-layout only).

By Transfers Tab

The By Transfers tab of the timing analysis report for pre-layout and post-layout simulations rolls up the By Variation tab by combining identical transfers (same driver and receiver).

Column	Description
Setup Margin (ns)	Worst difference between receiver setup time for the transfer and the setup requirement in its timing model.
Hold Margin (ns)	Worst difference between receiver hold time for the transfer and the hold requirement in its timing model.
Min Etch Delay (ns)	Minimum etch delay for the transfer.
Max Etch Delay (ns)	Maximum etch delay for the transfer.
Transfer Net	The name of the transfer net.
Driver	Transfer net designator name of driving node.
Receiver	Transfer net designator name of receiving node.
Column	Contains the name of each variation group, with the column number for each variation group (pre-layout only).

By Variation Tab

Column	Description
Setup Margin (ns)	Worst difference between receiver setup time for the transfer and the setup requirement in its timing model.
Hold Margin (ns)	Worst difference between receiver hold time for the transfer and the hold requirement in its timing model.
R_min Etch Delay (ns)	Minimum rising etch delay for the transfer.
R_max Etch Delay (ns)	Maximum rising etch delay for the transfer.
F_min Etch Delay (ns)	Minimum falling etch delay for the transfer.
F_max Etch Delay (ns)	Maximum falling etch delay for the transfer.
Transfer Net	The name of the transfer net.
Column	Contains the name of each variation group, with the column number for each variation group (pre-layout only).
Extended Net	The name of the extended net being simulated (post-layout only).
AC Noise	AC Noise entered in the product (pre-layout).
AC Noise Source	AC Noise Source selected in pre-layout.
$<variable_name>	Column for each variable used in variation group in the Solution Space panel (pre-layout only).

By Variation Details Tab

The By Variation Details tab of the timing analysis report for pre-layout and post-layout simulations contains the setup and hold margins for both rising and falling edges at each receiver in each simulation.

Column	Description
Setup Margin (ns)	Worst difference between receiver setup time for the transfer and the setup requirement in its timing model.
Hold Margin (ns)	Worst difference between receiver hold time for the transfer and the hold requirement in its timing model.
R_min Etch Delay (ns)	Minimum rising edge etch delay.
R_max Etch Delay (ns)	Maximum rising edge etch delay.
F_min Etch Delay (ns)	Minimum falling edge etch delay.
F_max Etch Delay (ns)	Maximum falling edge etch delay.
Transfer Net	The name of the transfer net.
Driver	Transfer net designator name of driving node.
Receiver	Transfer Net designator name of receiving node.
Driver Pin	Pin of the driving node (post-layout only).
Receiver Pin	Pin of the receiving node (post-layout only).
Corner	Silicon and etch corners.
Column	Contains the name of each variation group, with the column number for each variation group (pre-layout only).
Extended Net	The name of the extended net being simulated (post-layout only).
AC Noise	AC Noise entered in the product (pre-layout).
AC Noise Source	AC Noise Source selected in pre-layout.
Simulation	Simulation results file name.
Model Format	<Driver model> <Receiver model>, each can be either I (IBIS) or SPICE.
$<variable_name>	Column for each variable used in variation group in the Solution Space panel (pre-layout only).

By Variation Details Summary Tab

The By Variation Details Summary tab contains two rows for each transfer net:

The smallest setup margin for that transfer net
The smallest hold margin for that transfer net

This tab indicates the nets with the worst-case setup and hold margins in testing. This tab is only available in post-layout simulations.

Column	Description
Margin	Setup or Hold
Setup Margin (ns)	Worst difference between receiver setup time for the transfer and the setup requirement in its timing model.
Hold Margin (ns)	Worst difference between receiver hold time for the transfer and the hold requirement in its timing model.
R_min Etch Delay (ns)	Minimum rising edge etch delay.
R_max Etch Delay (ns)	Maximum rising edge etch delay.
F_min Etch Delay (ns)	Minimum falling edge etch delay.
F_max Etch Delay (ns)	Maximum falling edge etch delay.
Transfer Net	The name of the transfer net.
Driver	Transfer net designator name of driving node.
Receiver	Transfer Net designator name of receiving node.
Driver Pin	Pin of the driving node (post-layout only).
Receiver Pin	Pin of the receiving node (post-layout only).
Corner	Silicon and etch corners.
Column	Contains the name of each variation group, with the column number for each variation group (pre-layout only).
Extended Net	The name of the extended net being simulated (post-layout only).
Simulation	Simulation results file name.
Model Format	<Driver model> <Receiver model>, each can be either I (IBIS) or SPICE.

By Driver Tab

The By Driver tab of the timing analysis report for pre-layout and post-layout simulations rolls up the By Variation tab by combining identical drivers.

Column	Description
Setup Margin (ns)	Worst difference between receiver setup time for the transfer and the setup requirement in its timing model.
Hold Margin (ns)	Worst difference between receiver hold time for the transfer and the hold requirement in its timing model.
Min Etch Delay (ns)	Minimum etch delay.
Max Etch Delay (ns)	Maximum etch delay.
Transfer Net	The name of the transfer net.
Driver	Transfer net designator name of driving node.
Column	Contains the name of each variation group, with the column number for each variation group (pre-layout only).

By Receiver Tab

The By Receiver tab of the timing analysis report for pre-layout and post-layout simulations rolls up the By Variation tab by combining identical receivers.

Column	Description
Setup Margin (ns)	Worst difference between receiver setup time for the transfer and the setup requirement in its timing model.
Hold Margin (ns)	Worst difference between receiver hold time for the transfer and the hold requirement in its timing model.
Min Etch Delay (ns)	Minimum etch delay.
Max Etch Delay (ns)	Maximum etch delay.
Transfer Net	The name of the transfer net.
Receiver	Transfer net designator name of receiving node.
Column	Contains the name of each variation group, with the column number for each variation group (pre-layout only).

Synchronous Details Tab

The Synchronous Details tab of the timing analysis report for pre-layout and post-layout simulations contains the setup and hold margin for rising and falling data edges in each simulation.

Column	Description
Setup Margin (ns)	Worst difference between receiver setup time for the transfer and the setup requirement in its timing model.
Hold Margin (ns)	Worst difference between receiver hold time for the transfer and the hold requirement in its timing model.
R / F	Rising or falling edge.
Transfer Net	The name of the transfer net.
Driver	Transfer net designator name of driving node.
Receiver	Transfer net designator name of receiving node.
Driver Pin	Board, reference designator, and pin of driving node (post-layout only).
Receiver Pin	Board, reference designator, and pin of receiving node (post-layout only).
UI (ns)	Bit time.
Min Data Etch Delay (ns)	Minimum data etch delay to the receiver for the transfer net and corner.
Max Data Etch Delay (ns)	Maximum data etch delay to the receiver for the transfer net and corner.
Min T_co (ns)	Minimum clock-to-driver output delay for standard load specified in the timing model.
Max T_co (ns)	Maximum clock-to-driver output delay for standard load specified in the timing model.
Setup (ns)	Minimum setup time required by the receiver specified in the timing file.
Hold (ns)	Minimum hold time required by the receiver specified in the timing file.
Setup Skew (ns)	Maximum clock skew adversely affecting setup.
Hold Skew (ns)	Maximum clock skew adversely affecting hold.
Source Clock Pin	The board, reference designator, and pin number of the source clock when the clock skew is derived from simulation (post-layout only).
Target Clock Pin	The board, reference designator, and pin number of the target clock when the clock skew is derived from simulation (post-layout only).
Source Clock Net	The transfer net (pre-layout) or net (post-layout) of the source clock when the clock skew is derived from simulation.
Target Clock Net	The transfer net (pre-layout) or net (post-layout) of the target clock when the clock skew is derived from simulation.
Simulation	Name of simulation results file.
Model Format	Whether driver/receiver model is SPICE or IBIS.
Corner	Silicon and etch corners.

Source Synchronous Details Tab

The Source Synchronous Details tab of the timing analysis report for pre-layout and post-layout simulations contains the setup and hold margin for rising and falling data edges in each simulation.

Column	Description
Setup Margin (ns)	Worst difference between receiver setup time for the transfer and the setup requirement in its timing model.
Hold Margin (ns)	Worst difference between receiver hold time for the transfer and the hold requirement in its timing model.
R / F	Rising or falling edge.
Transfer Net	The name of the transfer net.
Driver	Transfer net designator name of driving node.
Receiver	Transfer net designator name of receiving node.
Driver Pin	Board, reference designator, and pin of driving node (post-layout only).
Receiver Pin	Board, reference designator, and pin of receiving node (post-layout only).
UI (ns)	Bit time.
Min Data Etch Delay (ns)	Minimum data etch delay to the receiver for the transfer net and corner.
Max Data Etch Delay (ns)	Maximum data etch delay to the receiver for the transfer net and corner.
R_min Clock Etch Delay (ns)	Minimum clock etch delay for rising edge for the transfer net.
R_max Clock Etch Delay (ns)	Maximum clock etch delay for rising edge for the transfer net.
F_min Clock Etch Delay (ns)	Minimum clock etch delay for falling edge for the transfer net.
F_max Clock Etch Delay (ns)	Maximum clock etch delay for falling edge for the transfer net.
R Setup (ns)	Minimum setup time (from the timing file) required by the receiver for a rising clock edge.
F Setup (ns)	Minimum setup time (from the timing file) required by the receiver for a falling clock edge.
R Hold (ns)	Minimum hold time (from the timing file) required by the receiver for a rising clock edge.
F Hold (ns)	Minimum hold time (from the timing file) required by the receiver for a falling clock edge.
R_min Delay Skew (ns)	Minimum delay of data driver output reference rising edge of clock driver output.
R_max Delay Skew (ns)	Maximum delay of data driver output reference rising edge of clock driver output.
F_min Delay Skew (ns)	Minimum delay of data driver output reference falling edge of clock driver output.
F_max Delay Skew (ns)	Maximum delay of data driver output reference falling edge of clock driver output.
Jitter	Timing uncertainty of clock due to jitter.
Simulation	Name of the simulation results file.
Strobe TNET	Net name of the signal that clocks data.
Strobe XNET	Extended net name of the (post-layout only).
Model Format	Whether driver/receiver model is SPICE or IBIS.
Corner	Silicon and etch corners.

Dynamic Clock Skew Tab

The Dynamic Clock Skew tab of the timing analysis report for pre-layout and post-layout simulations lists the skews between the clock pins used in synchronous timing analysis.

Column	Description
Source Clock Input Pin	Source clock receiving pin designator (pre-layout) or pin (post-layout).
Target Clock Input Pin	Target clock receiving pin designator (pre-layout) or pin (post-layout).
Setup Skew (ns)	Minimum interconnect delay difference between the source clock pin and the target clock pin. The delay is corrected by the minimum clock skew between the clock distribution source pin.
Hold Skew (ns)	Maximum interconnect delay difference between the source clock pin and the target clock pin. The delay is corrected by the maximum clock skew between the clock distribution source pin.

Dynamic Clock Skew Details Tab

The Dynamic Clock Skew Details tab of the timing analysis report for pre-layout and post-layout simulations lists the source pins and calculations that are used to create the skews between the clock pins used in synchronous timing analysis.

Column	Description
Part	Part name.
Source Net	Transfer net name (pre-layout) or net (post-layout) of source clock input pin.
Target Net	Transfer net name (pre-layout) or net (post-layout) of target clock input pin.
Source Pindef	Name of the timing group in the timing model for the source clock driving pin.
Target Pindef	Name of the timing group in the timing model for the target clock driving pin.
Source Pin	Source clock driving pin name.
Target Pin	Target clock driving pin name.
Corner	Silicon and etch corners.
Edge	R (rising) or F (falling).
Source Pin Target	Source clock receiving pin. In post-layout, it denotes the board, reference designator, and pin number. In pre-layout, it denotes the part and pin name.
Target Pin Target	Target clock receiving pin. In post-layout, it denotes the board, reference designator, and pin number. In pre-layout, it denotes the part and pin name.
Setup Skew (ns)	Setup skew between the source receiving pin and target receiving pin.
Hold Skew (ns)	Hold skew between the source receiving pin and target receiving pin.
R_min Skew (ns)	Rising edge minimum skew between the source receiving pin and target receiving pin.
R_max Skew (ns)	Rising edge maximum skew between the source receiving pin and target receiving pin.
F_min Skew (ns)	Falling edge minimum skew between the source receiving pin and target receiving pin.
F_max Skew (ns)	Falling edge maximum skew between the source receiving pin and target receiving pin.
R_min Source Clock Etch Delay (ns)	Rising edge minimum interconnect delay to the source receiving pin.
R_max Source Clock Etch Delay (ns)	Rising edge maximum interconnect delay to the source receiving pin.
F_min Source Clock Etch Delay (ns)	Falling edge minimum interconnect delay to the source receiving pin.
F_max Source Clock Etch Delay (ns)	Falling edge maximum interconnect delay to the source receiving pin.
R_min Target Clock Etch Delay (ns)	Rising edge minimum interconnect delay to the target receiving pin.
R_max Target Clock Etch Delay (ns)	Rising edge maximum interconnect delay to the target receiving pin.
F_min Target Clock Etch Delay (ns)	Falling edge minimum interconnect delay to the target receiving pin.
F_max Target Clock Etch Delay (ns)	Falling edge maximum interconnect delay to the target receiving pin.
Jitter	Setup correction for clock jitter.

No Strobe Details Tab

The No Strobe Details tab of the timing analysis report for post-layout simulations contains the details of source-synchronous constraints that do not have a strobe.

Column	Description
Net	Extended net that is the data net with no strobe.
Transfer Net	Transfer net that is the data net with no strobe.
Simulation	Name of the simulation results file.
Driver Part	MathWorks Part name of the driver.
Driver Designator	Designator name of the driver.
Driver Pin	Board, reference designator, and pin number of the driver.
Receiver Part	MathWorks Part name of the receiver.
Receiver Designator	Designator name of the receiver.
Receiver Pin	Board, reference designator, and pin number of the receiver.
Strobe Tnet	Transfer net name for the strobe.
Strobe Source Nets	Potential strobe nets with simulated transfers based on timing model `DELAY_SKEW` statements of the driver pin.
Strobe Target Nets	Potential strobe nets with simulated transfers based on timing model `DELAY_SKEW` statements of the receiver pin.
Strobe Nets	Nets that are potential strobe nets but do have not been simulated or do not have a simulation at the required corner.

Coupling Pushout Tab

The Coupling Pushout tab of the timing analysis report for pre-layout and post-layout simulations contains the coupling effects on timing.

Column	Description
Min Baseline Rise (ns)	Minimum rising edge etch delay at the mid point of receiver measurement range when aggressors are quiescent.
Max Baseline Rise (ns)	Maximum rising edge etch delay at the mid point of receiver measurement range when aggressors are quiescent.
Min Baseline Fall (ns)	Minimum falling edge etch delay at the mid point of receiver measurement range when aggressors are quiescent.
Max Baseline Fall (ns)	Maximum falling edge etch delay at the mid point of receiver measurement range when aggressors are quiescent.
Min Odd Rise Pushout (ns)	Change in the minimum rising edge delay at the mid point of receiver measurement range due to the aggressor switching in anti-phase to the victim.
Max Odd Rise Pushout (ns)	Change in the maximum rising edge delay at the mid point of receiver measurement range due to the aggressor switching in anti-phase to the victim.
Min Odd Fall Pushout (ns)	Change in the minimum falling edge delay at the mid point of receiver measurement range due to the aggressor switching in anti-phase to the victim.
Max Odd Fall Pushout (ns)	Change in the maximum falling edge delay at the mid point of receiver measurement range due to the aggressor switching in anti-phase to the victim.
Min Even Rise Pushout (ns)	Change in the minimum rising edge delay at the mid point of receiver measurement range due to the aggressor switching in phase to the victim.
Max Even Rise Pushout (ns)	Change in the maximum rising edge delay at the mid point of receiver measurement range due to the aggressor switching in phase to the victim.
Min Even Fall Pushout (ns)	Change in the minimum falling edge delay at the mid point of receiver measurement range due to the aggressor switching in phase to the victim.
Max Even Fall Pushout (ns)	Change in the maximum falling edge delay at the mid point of receiver measurement range due to the aggressor switching in phase to the victim.
Transfer Net	The name of the transfer net.
Driver	Transfer net designator name of the driving node.
Receiver	Transfer net designator name of the receiving node.
Simulation	The name of the simulation results file.
Corner	Silicon and etch corner.
$<variable name>	Column for each variable used in variation group in the Solution Space panel (pre-layout only).
Coupled Model	Name of the coupled W-element model.
SSO_Capacitance	On-die proportioned capacitance between V_ddq and V_ss.

Coupling Noise Tab

The Coupling Noise tab of the timing analysis report for pre-layout and post-layout simulations contains the voltage variation on victim nets caused by coupling.

Column	Description
Noise (V)	Maximum change in voltage due to the aggressor switching.
Baseline Voltage (V)	Voltage when the aggressors are not switching.
Min Voltage (V)	Minimum voltage reached when the aggressors are switching.
Max Voltage (V)	Maximum voltage reached when the aggressors are switching.
Min Time (ns)	The beginning of the simulation time window where min/max voltage is measured.
Max Tiime (ns)	The end of the simulation time window where min/max voltage is measured.
R / F	Rising or falling aggressor edge; high or low victim state.
Transfer Net	The name of the transfer net.
Driver	Transfer net designator name of the driving node.
Receiver	Transfer net designator name of the receiving node.
Simulation	The name of the simulation results file.
Corner	Silicon and etch corner.
$<variable name>	Column for each variable used in variation group in the Solution Space panel (pre-layout only).
Coupled Model	Name of the coupled W-element model.
SSO_Capacitance	On-die proportioned capacitance between V_ddq and V_ss.

Edge Details Tab

The Edge Details tab of the timing analysis report for pre-layout and post-layout simulations summarizes each edge in each simulation.

Column	Description
Transfer Net	The name of the transfer net.
Driver	Transfer net designator name of the driving node.
Receiver	Transfer net designator name of the receiving node.
Driver Pin	Board, reference designator, and pin of the driving node (post-layout only).
Receiver Pin	Board, reference designator, and pin of the receiving node (post-layout only).
R / F	Rising or falling edge.
Min Etch Delay (ns)	Minimum etch delay with respect to the reference.
Max Etch Delay (ns)	Maximum etch delay with respect to the reference.
AC-DC Slew Rate (V/ns)	Slew rate at the receiver.
Corner	Silicon and etch corner.
Edge #	Transition number of the stimulus.
Time (ns)	Time point in waveform where edge occurs.
UI (ns)	Bit time.
Delay Variation (ns)	Difference between the minimum and maximum delay.
Driver Probe Point	Driver probe point: `SL_pin`, `SL_pad` or `core`.
Receiver Node	The receiver node for this transfer.
Min Derate (ns)	Time minimum delay derated.
Max Derate (ns)	Time maximum delay derated.
Simulation	The name of the simulation results file.
Min Etch Raw Delay (ns)	Minimum delay measured before standard load compensation.
Max Etch Raw Delay (ns)	Maximum delay measured before standard load compensation.
Standard Load Delay (ns)	Standard load delay to subtract for this driver, process corner and edge.
Net (post layout)	Name of the net being simulated (post-layout only).
Column	Column in the Solution Space panel used (pre-layout only).
Ac Noise	AC Noise for this net.
Ac Noise Source	Source for AC noise.
Aggressor Separation	Aggressor Separation for w-lines (SSO analysis only).
$<variable name>	Column for each variable used in variation group in the Solution Space panel (pre-layout only).
SSO_Capacitance	On-die proportioned capacitance between V_ddq and V_ss (SSO analysis only).