dsphdl.ChannelSynthesizer

Combine narrowband signals into multichannel signal

Since R2021b

Description

The dsphdl.ChannelSynthesizer System object™ combines narrowband signals into a multi-channel signal using the polyphase filter bank technique. The filter bank uses a prototype lowpass filter and is implemented using a polyphase structure. You can specify the filter coefficients directly or through design parameters. The System object provides an architecture suitable for HDL code generation and hardware deployment.

The System object supports real and complex fixed-point inputs.

To combine multiple narrowband signals into a broadband signal:

1. Create the dsphdl.ChannelSynthesizer object and set its properties.

2. Call the object with arguments, as if it were a function.

To learn more about how System objects work, see What Are System Objects?

Note

You can also generate HDL code for this hardware-optimized algorithm, without creating a MATLAB^® script, by using the DSP HDL IP Designer app. The app provides the same interface and configuration options as the System object.

Creation

Syntax

ChannelSynthesizer = dsphdl.ChannelSynthesizer

ChannelSynthesizer = dsphdl.ChannelSynthesizer(Name=Value)

Description

ChannelSynthesizer = dsphdl.ChannelSynthesizer creates a polyphase FFT synthesis filter bank System object, which combines multiple narrowband input signals into a broadband output signal.

ChannelSynthesizer = dsphdl.ChannelSynthesizer(Name=Value) creates a polyphase FFT synthesis filter bank object with properties set using one or more name-value arguments.

Properties

Unless otherwise indicated, properties are nontunable, which means you cannot change their values after calling the object. Objects lock when you call them, and the release function unlocks them.

If a property is tunable, you can change its value at any time.

For more information on changing property values, see System Design in MATLAB Using System Objects.

Main

FilterCoefficients — Polyphase filter coefficients

[-0.0329 0.1218 0.3183 0.4829 0.5469 0.4829 0.5469 0.4829 0.3183 0.1218 -0.0329] (default) | real- or complex-valued vector

Polyphase filter coefficients, specified as a real- or complex-valued vector. If the number of coefficients is not a multiple of the number of frequency bands or the IFFT length, the object pads this vector with zeros. The default filter specification is a raised-cosine FIR filter, rcosdesign(0.25,2,4,'sqrt'). You can specify a vector of coefficients or a call to a filter design function that returns the coefficient values. By default, the object casts the coefficients to the same data type as the input.

FilterStructure — HDL filter architecture

'Direct form transposed' (default) | 'Direct form systolic'

HDL filter architecture, specified as one of these structures:

• Direct form transposed — This architecture is a fully parallel implementation that is suitable for FPGA and ASIC applications. For architecture details, see Fully Parallel Transposed Architecture.

• Direct form systolic — This architecture provides a fully parallel filter implementation that makes efficient use of Intel^® and AMD^® DSP blocks. For architecture details, see Fully Parallel Systolic Architecture.

ComplexMultiplication — HDL implementation of complex multipliers

'Use 4 multipliers and 2 adders' (default) | 'Use 3 multipliers and 5 adders'

HDL implementation of complex multipliers, specified as either 'Use 4 multipliers and 2 adders' or 'Use 3 multipliers and 5 adders'. The performance of the HDL implementation depends on your synthesis tool and target device.

Normalize — IFFT scaling

true or 1 (default) | false or 0

IFFT output scaling, specified as either:

• true — The IFFT implements an overall 1/N scale factor by scaling the result of each pipeline stage by 2, , where N is the IFFT length. This adjustment keeps the output of the IFFT in the same amplitude range as its input.

• false — The IFFT avoids overflow by increasing the word length by one bit at each stage.

Data Types

RoundingMethod — Rounding mode used for internal fixed-point calculations

'Floor' (default) | 'Ceiling' | 'Convergent' | 'Nearest' | 'Round' | 'Zero'

Rounding method for type-casting the output, specified as 'Floor', 'Ceiling', 'Convergent', 'Nearest', 'Round', or 'Zero'. The object uses this property when casting the output to the data type specified by the OutputDataType property. When the input data type is floating point, the object ignores this property. For more details, see Rounding Modes.

OverflowAction — Overflow handling for type-casting the output

'Wrap' (default) | 'Saturate'

Overflow handling for type-casting the output, specified as 'Wrap' or 'Saturate'. The object uses this property when casting the output to the data type specified by the OutputDataType property. When the input data type is floating point, the object ignores this property. For more details, see Overflow Handling.

The IFFT algorithm avoids overflow by either scaling the output of each stage (Normalize enabled), or by increasing the word length by 1 bit at each stage (Normalize disabled).

CoefficientsDataType — Data type of filter coefficients

'Same word length as input' (default) | numerictype object

Data type of filter coefficients, specified as 'Same word length as input' or a numerictype object. To specify a numerictype object, call numerictype(s,w,f), where:

• s is 1 for signed and 0 for unsigned.

• w is the word length in bits.

• f is the number of fractional bits.

The object casts the filter coefficients to the specified data type. The quantization rounds to the nearest representable value and saturates on overflow. When the input data type is floating point, the object ignores this property.

OutputDataType — Output data type

'Full precision' (default) | 'Same as input' | numerictype object

Output data type, specified as 'Same word length as input', 'Full precision', or a numerictype object. To specify a numerictype object, call numerictype(s,w,f), where:

• s is 1 for signed and 0 for unsigned.

• w is the word length in bits.

• f is the number of fractional bits.

The object casts the output of the filter to the specified data type. The quantization uses the settings of the RoundingMethod and OverflowAction properties. When the input data type is floating point, the object ignores this property.

When you set this property to 'Full precision', the System object selects a best-precision binary point by considering the values of your filter coefficients and the range of your input data type. When you set this property to 'Same as input', the System object casts the output of the polyphase filter to the input data type using the rounding and overflow settings you specify.

Control Arguments

ResetInputPort — Option to enable reset input argument

false (default) | true

Option to enable reset input argument, specified as true or false. When you set this property to true, the object expects a value for the reset input argument. The reset signal implements a local synchronous reset of the data path registers.

For more reset considerations, see the Reset Signal section on the Hardware Control Signals page.

Usage

Syntax

[dataOut,validOut] = channelsynthesizer(dataIn,validIn)

[dataOut,validOut] = channelsynthesizer(dataIn,validIn,reset)

Description

[dataOut,validOut] = channelsynthesizer(dataIn,validIn) combines the narrowband row input dataIn vector signals and returns a broadband signal, dataOut, when validIn is 1 (true). The validIn and validOut arguments are logical scalars that indicate the validity of the input and output signals, respectively.

[dataOut,validOut] = channelsynthesizer(dataIn,validIn,reset) combines the narrowband row input dataIn vector signals returns a broadband signal, dataOut, when validIn is 1 (true) and reset is 0 (false). When reset is 1 (true), the object stops the current calculation and clears all internal state.

To use this syntax, set the ResetInputPort property to true. For example:

synthesizer = dsphdl.ChannelSynthesizer(...,ResetInputPort=true);
...
[dataOut,validOut] = synthesizer(dataIn,validIn,reset)

Input Arguments

dataIn — Input data

real-valued row vector | complex-valued row vector

Input data, specified as a real-valued or complex-valued row vector.

The vector length must be a power of 2 and in the range [4, 64].

The software supports double and single data types for simulation, but not for HDL code generation.

Data Types: single | double | int8 | int16 | int32 | uint8 | uint16 | uint32 | fi
Complex Number Support: Yes

validIn — Indicates valid input data

scalar

Control signal that indicates if the input data is valid. When validIn is 1 (true), the object captures the values from the dataIn argument. When validIn is 0 (false), the object ignores the values from the dataIn argument.

Data Types: logical

reset — Clears internal states

logical scalar

Control signal that clears internal states. When reset is 1 (true), the object stops the current calculation and clears internal states. When the reset is 0 (false) and the input valid is 1 (true), the object captures data for processing.

For more reset considerations, see the Reset Signal section on the Hardware Control Signals page.

Dependencies

To enable this argument, set ResetInputPort to true.

Data Types: logical

Output Arguments

dataOut — Synthesized output data

complex-valued column vector

Synthesized output data, returned as a complex-valued column vector.

When the input data type is a floating-point type, the output data inherits the data type of the input data. When the input data type is an integer type or a fixed-point type, the OutputDataType property controls the data type of output data.

The output size is same as the input size and it is equal to the number of frequency bands or IFFT length.

The output order is bit natural. The output data type is a result of the bit growth in the IFFT necessary to avoid overflow and the data type set in the OutputDataType property.

Data Types: single | double | fi
Complex Number Support: Yes

validOut — Indicates valid output data

scalar

Control signal that indicates if the output data is valid. When validOut is 1 (true), the object returns valid data from the dataOut argument. When validOut is 0 (false), values from the dataOut argument are not valid.

Data Types: logical

Object Functions

To use an object function, specify the System object as the first input argument. For example, to release system resources of a System object named obj, use this syntax:

release(obj)

Specific to dsphdl.ChannelSynthesizer

getLatency

Latency of channel synthesizer calculation

Common to All System Objects

step	Run System object algorithm
release	Release resources and allow changes to System object property values and input characteristics
reset	Reset internal states of System object

Examples

Create Synthesizer for HDL Generation

Create a function that contains a channel synthesizer object and supports HDL code generation.

Create an input sine wave signal with the specified number of frequency bands, frequency vector, and loop count.

numOfFrequencyBands = 8;
frequency = [-250,-180,-120,50,120,175,230,300];
loopCount = 64;
sinewave = dsp.SineWave(ComplexOutput=true, ...
    Frequency=frequency, ...
   SamplesPerFrame=loopCount);
sa = spectrumAnalyzer(ShowLegend=true, ...
    SampleRate=sinewave.SampleRate*numOfFrequencyBands);

Call the function that contains the dsphdl.ChannelSynthesizer object. You can generate HDL code using this function.

function [yOut,validOut] = HDLSynthesizer8(yIn,validIn)
%HDLSynthesizer8 
% Combines narrow band signals to broadband signal using the
% |dsphdl.ChannelSynthesizer| System object(TM).

% |yIn| is a fixed-point row vector and |validIn| is a logical scalar value. 
% You can generate HDL code from this function.

  persistent synthesizer8;
  coder.extrinsic('tf');
  coder.extrinsic('dsp.Channelizer');
  
  if isempty(synthesizer8)
    % Use filter coefficients from non-HDL channelizer. You can also
    % provide your own filter coefficients.
    FilterCoefficients = tf(dsp.Channelizer( ...
        NumFrequencyBands=8));
    synthesizer8 = dsphdl.ChannelSynthesizer( ...
        FilterCoefficients=FilterCoefficients);
  end    
  [yOut,validOut] = synthesizer8(yIn,validIn);
end

% Copyright 2021-2023 The MathWorks, Inc.

Synthesize the input data by calling the function.

y = zeros(numOfFrequencyBands,loopCount);
validOut = false(loopCount,1);

for i  = 1:10
    x = fi(sinewave(),1,16); % Each column is a sine wave signal
    for j = 1:loopCount
        [y(:,j),validOut(j)] = HDLSynthesizer8(x(j,:),true);
    end
    yValid = y(:,validOut == true);
    sa(yValid(:));
end

Explore Latency of Channel Synthesizer Object

The latency of the dsphdl.ChannelSynthesizer object varies with the IFFT length and filter structure.

Create a dsphdl.ChannelSynthesizer object with a direct form transposed filter structure and 16 frequency bands, and then calculate the latency.

synthesizerDT = dsphdl.ChannelSynthesizer(FilterStructure='Direct form transposed');
latencyDT = getLatency(synthesizerDT,16)

latencyDT = 
20

Calculate the latency information for dsphdl.ChannelSynthesizer object with a direct form systolic filter structure and 8 frequency bands.

synthesizerDS = dsphdl.ChannelSynthesizer(FilterStructure='Direct form systolic');
latencyDS = getLatency(synthesizerDS,8)

latencyDS = 
21

Enable scaling at each stage of the IFFT. The latency does not change.

synthesizerDS.Normalize = true;
latencyDSn = getLatency(synthesizerDS,8)

latencyDSn = 
21

Algorithms

The polyphase filter algorithm requires a subfilter for each FFT channel. For more information on the polyphase filter architecture, see the Channelizer (DSP System Toolbox) block reference page.

If the FFT length is N, the object implements N subfilters in the hardware. Each subfilter is an FIR filter direct form transposed or direct form systolic with Num_Coeffs/N taps. The object casts the output of the subfilters to the specified OutputDataType property by using the rounding and overflow settings you select and then pipelines filter tap in the subfilter to target the DSP sections of an FPGA.

Latency

The latency varies with the input size and the filter structure. Use the getLatency function to find the latency of a particular configuration. Latency is the number of cycles between the first valid input and the first valid output, assuming that the input is continuous. The filter coefficients and complex multiplication do not affect the latency.

This figure shows the output of the object for a vector input length 8 when you set the FilterStructure property to 'Direct form transposed' and with other properties set to default values. The latency of the object is 19 clock cycles.

This figure shows the output of the object for a vector input of length 8 when you set the FilterStructure property to 'Direct form systolic' and with other properties set with default values. The latency of the object is 31 clock cycles.

Performance

These resource and performance data are the place-and-route results from the generated HDL targeted to the AMD Zynq^®- 7000 ZC706 evaluation board. The two examples in the tables use this common configuration:

• 1-by-8 vector

• 16-bit complex input data

• Filter structure — Direct form transposed

• Filter length — 96 coefficients

• Coefficient data type — Same word length as input

• Output data type — Same as input

• Complex multiplication (default) — Use 4 multipliers and 2 adders

• Output scaling — Enabled

The performance of the synthesized HDL code varies with your target and synthesis options.

When you set the FilterStructure property to 'Direct form transposed', the design achieves a clock frequency of 382 MHz. The design uses these resources.

Resource	Number Used
LUT	1953
FFS	3833
AMD LogiCORE® DSP48	208

When you set the Filter structure property to 'Direct form systolic', the design achieves a clock frequency of 381 MHz. The design uses these resources.

Resource	Number Used
LUT	2026
FFS	3519
AMD LogiCORE DSP48	208

References

[1] Harris, Fredric J. Multirate Signal Processing for Communication Systems. Upper Saddle River, N.J: Prentice Hall PTR, 2004.

[2] Harris, Frederic J., Chris Dick, and Michael Rice. "Digital Receivers and Transmitters Using Polyphase Filter Banks for Wireless Communications." IEEE^® Transactions on Microwave Theory and Techniques. 51, no 4, (April 2003): 1395–1412. https://doi.org/10.1109/TMTT.2003.809176.

Extended Capabilities

C/C++ Code Generation

Generate C and C++ code using MATLAB® Coder™.

This System object supports C/C++ code generation for accelerating MATLAB simulations, and for DPI component generation.

HDL Code Generation

Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

The software supports double and single data types for simulation, but not for HDL code generation.

To generate HDL code from predefined System objects, see HDL Code Generation from Viterbi Decoder System Object (HDL Coder).

Version History

Introduced in R2021b