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Autogenerated VHDL for FPGA - In - The Loop DUT I/O Issue "** HDL Parser Error: line XX: near "vector_of_std_logic_vector32", found unsupported data-type "vector_of_std_logic_vector32""
I have a Simulink model with rather complicated (and numerous) inputs and outputs. The current set up groups these connectors to...
7 years ago | 1 answer | 0
