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aijaz


Last seen: 8 days ago |  Active since 2023

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integerating the FPGA through the Matlab
the bitstream does not exist. please check the external console to make sure the bitstream generation os completed and try again...

15 days ago | 0 answers | 0

0

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Question


issue in IP core generation
Failed 'C:\Users\aijaz_22011140\OneDrive - Universiti Teknologi PETRONAS\Desktop' contains white space in project path. Please t...

20 days ago | 1 answer | 0

1

answer

Question


echo is off issue in matlab
Task "Vivado IP Packager" unsuccessful. See log for details. Generated logfile: ECHO is off. ECHO is off. while generatin...

20 days ago | 0 answers | 0

0

answers

Question


HDL Tool setup issue
hdlsetuptoolpath('ToolName','Xilinx Vivado','ToolPath',... 'E:\Xilinx\Vivado\2023.1\bin\vivado.bat'); Error using setupToolPa...

2 months ago | 2 answers | 0

2

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Question


facing a error while implementing the HDL?
For the block 'untitled/controller/Discrete fractional Transfer Fcn4/Discrete Zero-Pole' Block 'untitled/controller/Discrete fra...

4 months ago | 1 answer | 1

1

answer

Question


how to compatible xilinx wth matlab.
I am trying to connect the xilinx vivado with matlab. it gives error of the path directory. as well as i am tying to open the sy...

6 months ago | 1 answer | 0

1

answer

Answered
RTL generation error: Signal rate of value inf found
ErrorNative floating-point code generation cannot complete for the following reason(s): 'PID_controller12/controller Signal ra...

9 months ago | 0