HDL Verifier SystemVerilog DPI component generation with Synopsys VCS

Generate SystemVerilog DPI component from MATLAB for Synopsys VCS simulation

This example was used in the video demonstration:
https://www.mathworks.com/videos/generate-systemverilog-dpi-components-for-simulation-with-synopsys-vcs-1495725854304.html
It illustrates how to re-use MATLAB functions and stimulus to more quickly build a Universal Verification Methodology testbench. Specifically it generates SystemVerilog DPI components from a MATLAB algorithm for use in a UVM scoreboard, and for a realistic video input for use as a UVM sequence item. The simulation is set up to run Synopsys VCS.