Error in importhdl how to solve?

I am trying to import a verilog module that calls other submodules. Whenever, I try to import from HDL to simulink, I am getting these errors. I don't even any clock in my design.

Module instance creation failed for 'x' module and 'y' module instance, due to clock inference limitation. Rerun with clock bundle name-value pair. More information.

Hdl Import parse failed.

Error using privimporthdl

Importhdl failed.

Error in importhdl (line 78)

privimporthdl(hdlInSrc, varargin{:}) - Show complete stack trace

[Khalala Mamouri]

Hello,

I currently facing the same issue; have you solved the problem ?

Best regards

lakhdar

[Nadatimuj]

I found that I have used some posedge in my code. And also some variables that sound like clock and reset. Matlab thought those are real clocks. If it finds same clocks between the modules, it gives this error. I couldn't solve it though.

Answer 1

[Stefanie Schwarz]

Here is a list of supported constructs with importdhl:

https://www.mathworks.com/help/hdlcoder/ug/supported-verilog-constructs-for-hdl-import.html

If you encounter the same error, please contact MathWorks Technical Support with your Verilog source code so we can investigate.