How to have multiple clock inputs on IP Core generated by HDL Coder?
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I need to have 2 clock inputs on IP Core generated by HDL Coder.
Vivado allows it, but HDL Coder flags an error and demands to change settings to a single clock input.
Why would HDL Coder do that while Xilinx allows IP Core with multiple clock inputs?
Any adwise?
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on 13 Mar 2020
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