same input output signal name in simulink

I want to make code below by model (or stateflow) using Code Generation

if( var > 10){

var = 10;

}

In this case, upper 'var' is input of chart(or subsystem) and lower 'var' is output of chart.

So, it occurs signal complication if I use same variables name or I can't make same name of chart's input and output.

I can make this if sentance by using two variables, but I hope to make this by using one.

Thanks for your help.

Sincerely,

TaeHee Kwun.

Answer 1

[Phani Teja]

Yeh It can be possible with Data store memory block.

Make a Variable 'Var' in stateflow and change its scope to Data store memory .

You can also control the variable storage class by resolving data store memory with simulink signal.

The generated code looks like:

/* Real-time model */

RT_MODEL_Chart_T Chart_M_;

RT_MODEL_Chart_T *const Chart_M = &Chart_M_;

/* Model step function */

void Chart_step(void)

{

/* Chart: '<Root>/Chart' */

/* Re-use inputs */

if (Var > 10) {

/* NEW_PATTERN */

Var = 10;

}

/* End of Chart: '<Root>/Chart' */

}

[TaeHee Kwun]

Thanks for your answer!

But, I can't still understand how to make this blocks...

If you can, can you upload some of your blocks?

Thanks.

[sreedevi]

Hi ,Did you get an answer for the question.If yes please post it