This is a limitation of Simulink HDL Coder. You can not reasonably synthesize a device that takes a frame of data at a time as an input. Even a small image frame will contain many more bits of input than any FPGA has pins. Also, the hardware resource requirements for processing a frame at a time an a FPGA are extreme.
You will need to convert your Simulink design into a form that provides a serial bit-stream to your DUT. If you look at the Simulink HDL Coder examples, you can find examples of this in the Sobel Edge Detection example, and also in the Image Reconstruction example.