Can I perform FPGA in the Loop with SysGen for DSP without HDL Coder and Verifier ?

Hi,

For my internship I have to implement FPGA in the Loop in Matlab. I have a licence for System Generator for DSP but it's not possible to have a license for HDL Coder or HDL Verifier. If I have already my VHDL code, it's possible to perform FIL with only SysGen for DSP ?

Thank you in advance

Answer 1

[Arnav Mendiratta]

No, You would need HDL Verifier for FIL Simulations. You can request a 1 month trial for free.

[Yoni Levy]

Thanks for the answer