How can adder configuration be modified in Discrete FIR Filter (DSP System Toolbox HDL Coder Support)?

The Discrete FIR Filter defaults to a linear adder architecture with no pipelining, leading to large propagation delays. Is there a way to modify the architecture to implement an adder tree with pipelining?

Answer 1

[Rohit Jain]

You can try using the property 'AddPipelineRegisters'.

Refer to below doc for more details:

http://in.mathworks.com/help/releases/R2014b/hdlcoder/ug/hdl-filter-block-properties.html#buaslqi-1

http://in.mathworks.com/help/releases/R2014b/hdlcoder/ref/discretefirfilter.html

Hope this helps.