How to use FPGA multiplier efficiently?

I have a timing warning for my compiled HDL code and this is caused by a product block in my Simulink model.

The data type of both inputs is fixdt(1,32,16, 'DataTypeOverride', 'Off'). And both input signals to the product block are delayed by a delay block with an order of 1. This is also done for the output of the product block.

My assumption is that the realization of the product in the HDL generation is done unfavorable. So that the corresponding registers of a multiplier cell in my FPGA are not used and instead extern registers were used which leads to an unwanted delay and this causes the timing violation.

Is there a possibility to configure the product bloc in a way, that the FPGA multiplier cells are used efficiently?

Answer 1

[Bharath Venkataraman]

Can you see what kind of reset you used for the HDL code? You likely want to set the register to have synchronous reset - this can be done by going to the Configuration Parameters for the model, then going to the HDL Coder pane.

It may also help to reduce your multiplier width - typically, widths of 18 bits or less produce best timing results.

Another option is to increase the pipelining on both sides of the multiplier.

[Lutz]

What do you mean by "what kind of reset"? And it is not clear to me where to find the setting for the synchronous reset you mentioned.

And I am fixed to the input values of 32bit and can't reduce to 18bit. My hope was that the coder generates a smart architecture using 18bit multiplier cells to handle the 32bit value.

Answer 2

[Bharath Venkataraman]

Open the model, hit Ctrl-E and the Configuration Parameters dialog should open. Click into the HDL Code Generation section and go to Global Settings. You should see the Rest type under Clock settings.

The option to split into smaller multipliers was answered in this post: http://www.mathworks.com/matlabcentral/answers/224202-hdl-coder-pipelined-multipliers-in-logic

[Lutz]

Thanks for the instruction! At the moment I am using the asynchronous reset type.

And the link you send was very interesting, but unfortunately this feature isn't available in R2013b. The only things which I can set in this window are:

• Balance delays (checked)
• Hierarchical distributed pipelining (unchecked)
• Optimize timing controller (checked)
• minimize clock enables (unchecked)
• RAM mapping Threshold (256)
• Max oversampling (Inf)
• Max computation latency (1)

Do you have any other idea to fix this?